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    /* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H

/* DISP_CC clock registers */
#define DISP_CC_MDSS_AHB_CLK			0
#define DISP_CC_MDSS_AHB_CLK_SRC		1
#define DISP_CC_MDSS_BYTE0_CLK			2
#define DISP_CC_MDSS_BYTE0_CLK_SRC		3
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC		4
#define DISP_CC_MDSS_BYTE0_INTF_CLK		5
#define DISP_CC_MDSS_BYTE1_CLK			6
#define DISP_CC_MDSS_BYTE1_CLK_SRC		7
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC		8
#define DISP_CC_MDSS_BYTE1_INTF_CLK		9
#define DISP_CC_MDSS_DP_AUX1_CLK		10
#define DISP_CC_MDSS_DP_AUX1_CLK_SRC		11
#define DISP_CC_MDSS_DP_AUX_CLK			12
#define DISP_CC_MDSS_DP_AUX_CLK_SRC		13
#define DISP_CC_MDSS_DP_LINK1_CLK		14
#define DISP_CC_MDSS_DP_LINK1_CLK_SRC		15
#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC	16
#define DISP_CC_MDSS_DP_LINK1_INTF_CLK		17
#define DISP_CC_MDSS_DP_LINK_CLK		18
#define DISP_CC_MDSS_DP_LINK_CLK_SRC		19
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC	20
#define DISP_CC_MDSS_DP_LINK_INTF_CLK		21
#define DISP_CC_MDSS_DP_PIXEL1_CLK		22
#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC		23
#define DISP_CC_MDSS_DP_PIXEL2_CLK		24
#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC		25
#define DISP_CC_MDSS_DP_PIXEL_CLK		26
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC		27
#define DISP_CC_MDSS_ESC0_CLK			28
#define DISP_CC_MDSS_ESC0_CLK_SRC		29
#define DISP_CC_MDSS_ESC1_CLK			30
#define DISP_CC_MDSS_ESC1_CLK_SRC		31
#define DISP_CC_MDSS_MDP_CLK			32
#define DISP_CC_MDSS_MDP_CLK_SRC		33
#define DISP_CC_MDSS_MDP_LUT_CLK		34
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK		35
#define DISP_CC_MDSS_PCLK0_CLK			36
#define DISP_CC_MDSS_PCLK0_CLK_SRC		37
#define DISP_CC_MDSS_PCLK1_CLK			38
#define DISP_CC_MDSS_PCLK1_CLK_SRC		39
#define DISP_CC_MDSS_ROT_CLK			40
#define DISP_CC_MDSS_ROT_CLK_SRC		41
#define DISP_CC_MDSS_RSCC_AHB_CLK		42
#define DISP_CC_MDSS_RSCC_VSYNC_CLK		43
#define DISP_CC_MDSS_VSYNC_CLK			44
#define DISP_CC_MDSS_VSYNC_CLK_SRC		45
#define DISP_CC_PLL0				46
#define DISP_CC_PLL1				47
#define DISP_CC_MDSS_EDP_AUX_CLK		48
#define DISP_CC_MDSS_EDP_AUX_CLK_SRC		49
#define DISP_CC_MDSS_EDP_GTC_CLK		50
#define DISP_CC_MDSS_EDP_GTC_CLK_SRC		51
#define DISP_CC_MDSS_EDP_LINK_CLK		52
#define DISP_CC_MDSS_EDP_LINK_CLK_SRC		53
#define DISP_CC_MDSS_EDP_LINK_INTF_CLK		54
#define DISP_CC_MDSS_EDP_PIXEL_CLK		55
#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC		56

/* DISP_CC Reset */
#define DISP_CC_MDSS_CORE_BCR			0
#define DISP_CC_MDSS_RSCC_BCR			1

/* DISP_CC GDSCR */
#define MDSS_GDSC				0

#endif
     ˆ¿Æƒy°3¾ÅÈ !7    /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
 * Author: Shawn Lin <shawn.lin@rock-chips.com>
 */

#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H

/* pll id */
#define PLL_APLL			0
#define PLL_DPLL			1
#define PLL_GPLL			2
#define ARMCLK				3

/* sclk gates (special clocks) */
#define SCLK_SPI0			65
#define SCLK_NANDC			67
#define SCLK_SDMMC			68
#define SCLK_SDIO			69
#define SCLK_EMMC			71
#define SCLK_UART0			72
#define SCLK_UART1			73
#define SCLK_UART2			74
#define SCLK_I2S0			75
#define SCLK_I2S1			76
#define SCLK_I2S2			77
#define SCLK_TIMER0			78
#define SCLK_TIMER1			79
#define SCLK_SFC			80
#define SCLK_SDMMC_DRV			81
#define SCLK_SDIO_DRV			82
#define SCLK_EMMC_DRV			83
#define SCLK_SDMMC_SAMPLE		84
#define SCLK_SDIO_SAMPLE		85
#define SCLK_EMMC_SAMPLE		86
#define SCLK_VENC_CORE			87
#define SCLK_HEVC_CORE			88
#define SCLK_HEVC_CABAC			89
#define SCLK_PWM0_PMU			90
#define SCLK_I2C0_PMU			91
#define SCLK_WIFI			92
#define SCLK_CIFOUT			93
#define SCLK_MIPI_CSI_OUT		94
#define SCLK_CIF0			95
#define SCLK_CIF1			96
#define SCLK_CIF2			97
#define SCLK_CIF3			98
#define SCLK_DSP			99
#define SCLK_DSP_IOP			100
#define SCLK_DSP_EPP			101
#define SCLK_DSP_EDP			102
#define SCLK_DSP_EDAP			103
#define SCLK_CVBS_HOST			104
#define SCLK_HDMI_SFR			105
#define SCLK_HDMI_CEC			106
#define SCLK_CRYPTO			10