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Index of /anon_sym/anon/proc/thread-self/root/lib/locale/en_BW
Index of /anon_sym/anon/proc/thread-self/root/lib/locale/en_BW
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|"_I|+ # /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2015 Heiko Stuebner
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
/* core clocks */
#define PLL_APLLB 1
#define PLL_APLLL 2
#define PLL_DPLL 3
#define PLL_CPLL 4
#define PLL_GPLL 5
#define PLL_NPLL 6
#define ARMCLKB 7
#define ARMCLKL 8
/* sclk gates (special clocks) */
#define SCLK_GPU_CORE 64
#define SCLK_SPI0 65
#define SCLK_SPI1 66
#define SCLK_SPI2 67
#define SCLK_SDMMC 68
#define SCLK_SDIO0 69
#define SCLK_EMMC 71
#define SCLK_TSADC 72
#define SCLK_SARADC 73
#define SCLK_NANDC0 75
#define SCLK_UART0 77
#define SCLK_UART1 78
#define SCLK_UART2 79
#define SCLK_UART3 80
#define SCLK_UART4 81
#define SCLK_I2S_8CH 82
#define SCLK_SPDIF_8CH 83
#define SCLK_I2S_2CH 84
#define SCLK_TIMER00 85
#define SCLK_TIMER01 86
#define SCLK_TIMER02 87
#define SCLK_TIMER03 88
#define SCLK_TIMER04 89
#define SCLK_TIMER05 90
#define SCLK_OTGPHY0 93
#define SCLK_OTG_ADP 96
#define SCLK_HSICPHY480M 97
#define SCLK_HSICPHY12M