0 "1li~ *j"T Ɲ&Tţ h1DEVTYPE=usb_interface DRIVER=usbhid PRODUCT=627/1/0 TYPE=0/0/0 INTERFACE=3/0/0 MODALIAS=usb:v0627p0001d0000dc00dsc00dp00ic03isc00ip00in00 +3l4( (  fB- i_I|+0<3/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H #define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H #define GPLL0 0 #define GPLL0_MAIN 1 #define GCC_SLEEP_CLK_SRC 2 #define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 #define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 #define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 #define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 #define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 #define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 #define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 #define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 #define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 #define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 #define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 #define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 #define BLSP1_UART1_APPS_CLK_SRC 15 #define BLSP1_UART2_APPS_CLK_SRC 16 #define BLSP1_UART3_APPS_CLK_SRC 17 #define BLSP1_UART4_APPS_CLK_SRC 18 #define BLSP1_UART5_APPS_CLK_SRC 19 #define BLSP1_UART6_APPS_CLK_SRC 20 #define GCC_BLSP1_AHB_CLK 21 #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 #define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 #define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 #define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 #define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 #define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 #define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 #define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 #define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 #define GCC_BLSP1_UART1_APPS_CLK 34 #define GCC_BLSP1_UART2_APPS_CLK 35 #define GCC_BLSP1_UART3_APPS_CLK 36 #define GCC_BLSP1_UART4_APPS_CLK 37 #define GCC_BLSP1_UART5_APPS_CLK 38 #define GCC_BLSP1_UART6_APPS_CLK 39 #define GCC_PRNG_AHB_CLK 40 #define GCC_QPIC_AHB_CLK 41 #define GCC_QPIC_CLK 42 #define PCNOC_BFDCD_CLK_SRC 43 #define GPLL2_MAIN 44 #define GPLL2 45 #define GPLL4_MAIN 46 #define GPLL4 47 #define GPLL6_MAIN 48 #define GPLL6 49 #define UBI32_PLL_MAIN 50 #define UBI32_PLL 51 #define NSS_CRYPTO_PLL_MAIN 52 #define NSS_CRYPTO_PLL 53 #define PCIE0_AXI_CLK_SRC 54 #define PCIE0_AUX_CLK_SRC 55 #define PCIE0_PIPE_CLK_SRC 56 #define PCIE1_AXI_CLK_SRC 57 #define PCIE1_AUX_CLK_SRC 58 #define PCIE1_PIPE_CLK_SRC 59 #define SDCC1_APPS_CLK_SRC 60 #define SDCC1_ICE_CORE_CLK_SRC 61 #define SDCC2_APPS_CLK_SRC 62 #define USB0_MASTER_CLK_SRC 63 #define USB0_AUX_CLK_SRC 64 #define USB0_MOCK_UTMI_CLK_SRC 65 #define USB0_PIPE_CLK_SRC 66 #define USB1_MASTER_CLK_SRC 67 #define USB1_AUX_CLK_SRC 68 #define USB1_MOCK_UTMI_CLK_SRC 69 #define USB1_PIPE_CLK_SRC 70 #define GCC_XO_CLK_SRC 71 #define SYSTEM_NOC_BFDCD_CLK_SRC 72 #define NSS_CE_CLK_SRC 73 #define NSS_NOC_BFDCD_CLK_SRC 74 #define NSS_CRYPTO_CLK_SRC 75 #define NSS_UBI0_CLK_SRC 76 #define NSS_UBI0_DIV_CLK_SRC 77 #define NSS_UBI1_CLK_SRC 78 #define NSS_UBI1_DIV_CLK_SRC 79 #define UBI_MPT_CLK_SRC 80 #define NSS_IMEM_CLK_SRC 81 #define NSS_PPE_CLK_SRC 82 #define NSS_PORT1_RX_CLK_SRC 83 #define NSS_PORT1_RX_DIV_CLK_SRC 84 #define NSS_PORT1_TX_CLK_SRC 85 #define NSS_PORT1_TX_DIV_CLK_SRC 86 #define NSS_PORT2_RX_CLK_SRC 87 #define NSS_PORT2_RX_DIV_CLK_SRC 88 #define NSS_PORT2_TX_CLK_SRC 89 #define NSS_PORT2_TX_DIV_CLK_SRC 90 #define NSS_PORT3_RX_CLK_SRC 91 #define NSS_PORT3_RX_DIV_CLK_SRC 92 #define NSS_PORT3_TX_CLK_SRC 93 #define NSS_PORT3_TX_DIV_CLK_SRC 94 #define NSS_PORT4_RX_CLK_SRC 95 #define NSS_PORT4_RX_DIV_CLK_SRC 96 #define NSS_PORT4_TX_CLK_SRC 97 #define NSS_PORT4_TX_DIV_CLK_SRC 98 #define NSS_PORT5_RX_CLK_SRC 99 #define NSS_PORT5_RX_DIV_CLK_SRC 100 #define NSS_PORT5_TX_CLK_SRC 101 #define NSS_PORT5_TX_DIV_CLK_SRC 102 #define NSS_PORT6_RX_CLK_SRC 103 #define NSS_PORT6_RX_DIV_CLK_SRC 104 #define NSS_PORT6_TX_CLK_SRC 105 #define NSS