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Index of /FSS-OZR/root/sys/bus/acpi/devices/LNXSYBUS:00/PNP0A03:00/physical_node/firmware_node/device:00/subsystem
Index of /FSS-OZR/root/sys/bus/acpi/devices/LNXSYBUS:00/PNP0A03:00/physical_node/firmware_node/device:00/subsystem
* l4(
( fB-
u;_I|+ /* SPDX-License-Identifier: GPL-2.0-only */
/*
* MFD core driver for Richtek RT5033
*
* Copyright (C) 2014 Samsung Electronics, Co., Ltd.
* Author: Beomho Seo
*/
#ifndef __RT5033_PRIVATE_H__
#define __RT5033_PRIVATE_H__
enum rt5033_reg {
RT5033_REG_CHG_STAT = 0x00,
RT5033_REG_CHG_CTRL1 = 0x01,
RT5033_REG_CHG_CTRL2 = 0x02,
RT5033_REG_DEVICE_ID = 0x03,
RT5033_REG_CHG_CTRL3 = 0x04,
RT5033_REG_CHG_CTRL4 = 0x05,
RT5033_REG_CHG_CTRL5 = 0x06,
RT5033_REG_RT_CTRL0 = 0x07,
RT5033_REG_CHG_RESET = 0x08,
/* Reserved 0x09~0x18 */
RT5033_REG_RT_CTRL1 = 0x19,
/* Reserved 0x1A~0x20 */
RT5033_REG_FLED_FUNCTION1 = 0x21,
RT5033_REG_FLED_FUNCTION2 = 0x22,
RT5033_REG_FLED_STROBE_CTRL1 = 0x23,
RT5033_REG_FLED_STROBE_CTRL2 = 0x24,
RT5033_REG_FLED_CTRL1 = 0x25,
RT5033_REG_FLED_CTRL2 = 0x26,
RT5033_REG_FLED_CTRL3 = 0x27,
RT5033_REG_FLED_CTRL4 = 0x28,
RT5033_REG_FLED_CTRL5 = 0x29,
/* Reserved 0x2A~0x40 */
RT5033_REG_CTRL = 0x41,
RT5033_REG_BUCK_CTRL = 0x42,
RT5033_REG_LDO_CTRL = 0x43,
/* Reserved 0x44~0x46 */
RT5033_REG_MANUAL_RESET_CTRL = 0x47,
/* Reserved 0x48~0x5F */
RT5033_REG_CHG_IRQ1 = 0x60,
RT5033_REG_CHG_IRQ2 = 0x61,
RT5033_REG_CHG_IRQ3 = 0x62,
RT5033_REG_CHG_IRQ1_CTRL = 0x63,
RT5033_REG_CHG_IRQ2_CTRL = 0x64,
RT5033_REG_CHG_IRQ3_CTRL = 0x65,
RT5033_REG_LED_IRQ_STAT = 0x66,
RT5033_REG_LED_IRQ_CTRL = 0x67,
RT5033_REG_PMIC_IRQ_STAT = 0x68,
RT5033_REG_PMIC_IRQ_CTRL = 0x69,
RT5033_REG_SHDN_CTRL = 0x6A,
RT5033_REG_OFF_EVENT = 0x6B,
RT5033_REG_END,
};
/* RT5033 Charger state register */
#define RT5033_CHG_STAT_MASK 0x20
#define RT5033_CHG_STAT_DISCHARGING 0x00
#define RT5033_CHG_STAT_FULL 0x10
#define RT5033_CHG_STAT_CHARGING 0x20
#define RT5033_CHG_STAT_NOT_CHARGING 0x30
#define RT5033_CHG_STAT_TYPE_MASK 0x60
#define RT5033_CHG_STAT_TYPE_PRE 0x20
#define RT5033_CHG_STAT_TYPE_FAST 0x60
/* RT5033 CHGCTRL1 register */
#define RT5033_CHGCTRL1_IAICR_MASK 0xe0
#define RT5033_CHGCTRL1_MODE_MASK 0x01
/* RT5033 CHGCTRL2 register */
#define RT5033_CHGCTRL2_CV_MASK 0xfc
/* RT5033 CHGCTRL3 register */
#define RT5033_CHGCTRL3_CFO_EN_MASK 0x40