+l4( (  fB- ?_I|+'`/* SPDX-License-Identifier: GPL-2.0-only */ /* * Marvell 88PM80x Interface * * Copyright (C) 2012 Marvell International Ltd. * Qiao Zhou */ #ifndef __LINUX_MFD_88PM80X_H #define __LINUX_MFD_88PM80X_H #include #include #include #include enum { CHIP_INVALID = 0, CHIP_PM800, CHIP_PM805, CHIP_PM860, CHIP_MAX, }; enum { PM800_ID_BUCK1 = 0, PM800_ID_BUCK2, PM800_ID_BUCK3, PM800_ID_BUCK4, PM800_ID_BUCK5, PM800_ID_LDO1, PM800_ID_LDO2, PM800_ID_LDO3, PM800_ID_LDO4, PM800_ID_LDO5, PM800_ID_LDO6, PM800_ID_LDO7, PM800_ID_LDO8, PM800_ID_LDO9, PM800_ID_LDO10, PM800_ID_LDO11, PM800_ID_LDO12, PM800_ID_LDO13, PM800_ID_LDO14, PM800_ID_LDO15, PM800_ID_LDO16, PM800_ID_LDO17, PM800_ID_LDO18, PM800_ID_LDO19, PM800_ID_RG_MAX, }; #define PM800_MAX_REGULATOR PM800_ID_RG_MAX /* 5 Bucks, 19 LDOs */ #define PM800_NUM_BUCK (5) /*5 Bucks */ #define PM800_NUM_LDO (19) /*19 Bucks */ /* page 0 basic: slave adder 0x60 */ #define PM800_STATUS_1 (0x01) #define PM800_ONKEY_STS1 BIT(0) #define PM800_EXTON_STS1 BIT(1) #define PM800_CHG_STS1 BIT(2) #define PM800_BAT_STS1 BIT(3) #define PM800_VBUS_STS1 BIT(4) #define PM800_LDO_PGOOD_STS1 BIT(5) #define PM800_BUCK_PGOOD_STS1 BIT(6) #define PM800_STATUS_2 (0x02) #define PM800_RTC_ALARM_STS2 BIT(0) /* Wakeup Registers */ #define PM800_WAKEUP1 (0x0D) #define PM800_WAKEUP2 (0x0E) #define PM800_WAKEUP2_INV_INT BIT(0) #define PM800_WAKEUP2_INT_CLEAR BIT(1) #define PM800_WAKEUP2_INT_MASK BIT(2) #define PM800_POWER_UP_LOG (0x10) /* Referance and low power registers */ #define PM800_LOW_POWER1 (0x20) #define PM800_LOW_POWER2 (0x21) #define PM800_LOW_POWER_CONFIG3 (0x22) #define PM800_LOW_POWER_CONFIG4 (0x23) /* GPIO register */ #define PM800_GPIO_0_1_CNTRL (0x30) #define PM800_GPIO0_VAL BIT(0) #define PM800_GPIO0_GPIO_MODE(x) (x << 1) #define PM800_GPIO1_VAL BIT(4) #define PM800_GPIO1_GPIO_MODE(x) (x << 5) #define PM800_GPIO_2_3_CNTRL (0x31) #define PM800_GPIO2_VAL BIT(0) #define PM800_GPIO2_GPIO_MODE(x) (x << 1) #define PM800_GPIO3_VAL BIT(4) #define PM800_GPIO3_GPIO_MODE(x) (x << 5) #define PM800_GPIO3_MODE_MASK 0x1F #define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6) #define PM800_GPIO_4_CNTRL (0x32) #define PM800_GPIO4_VAL BIT(0) #define PM800_GPIO4_GPIO_MODE(x) (x << 1) #define PM800_HEADSET_CNTRL (0x38) #define PM800_HEADSET_DET_EN BIT(7) #define PM800_HSDET_SLP BIT(1) /* PWM register */ #define PM800_PWM1 (0x40) #define PM800_PWM2 (0x41) #define PM800_PWM3 (0x42) #define PM800_PWM4 (0x43) /* RTC Registers */ #define PM800_RTC_CONTROL (0xD0) #define PM800_RTC_MISC1 (0xE1) #define PM800_RTC_MISC2 (0xE2) #define PM800_RTC_MISC3 (0xE3) #define PM800_RTC_MISC4 (0xE4) #define PM800_RTC_MISC5 (0xE7) /* bit definitions of RTC Register 1 (0xD0) */ #define PM800_ALARM1_EN BIT(0) #define PM800_ALARM_WAKEUP BIT(4) #define PM800_ALARM BIT(5) #define PM800_RTC1_USE_XO BIT(7) /* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */ /* buck registers */ #define PM800_SLEEP_BUCK1 (0x30) /* BUCK Sleep Mode Register 1: BUCK[1..4] */ #define PM800_BUCK_SLP1 (0x5A) #define PM800_BUCK1_SLP1_SHIFT 0 #define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT) /* page 2 GPADC: slave adder 0x02 */ #define PM800_GPADC_MEAS_EN1 (0x01) #define PM800_MEAS_EN1_VBAT BIT(2) #define PM800_GPADC_MEAS_EN2 (0x02) #define PM800_MEAS_EN2_RFTMP BIT(0) #define PM800_MEAS_GP0_EN BIT(2) #define PM800_MEAS_GP1_EN BIT(3) #define PM800_MEAS_GP2_EN BIT(4) #define PM800_MEAS_GP3_EN BIT(5) #define PM800_MEAS_GP4_EN BIT(6) #define PM800_GPADC_MISC_CONFIG1 (0x05) #define PM800_GPADC_MISC_CONFIG2 (0x06) #define PM800_GPADC_MISC_GPFSM_EN BIT(0) #define PM800_GPADC_SLOW_MODE(x) (x << 3) #define PM800_GPADC_MISC_CONFIG3 (0x09) #define PM800_GPADC_MISC_CONFIG4 (0x0A) #define PM800_GPADC_PREBIAS1 (0x0F) #define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0) #d