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  *   ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿÂƒ.9_†I|¥�+ÂÅ 	>    /* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
 */

#ifndef _LINUX_NVME_RDMA_H
#define _LINUX_NVME_RDMA_H

#define NVME_RDMA_IP_PORT		4420

#define NVME_RDMA_MAX_QUEUE_SIZE 256
#define NVME_RDMA_MAX_METADATA_QUEUE_SIZE 128
#define NVME_RDMA_DEFAULT_QUEUE_SIZE 128

enum nvme_rdma_cm_fmt {
	NVME_RDMA_CM_FMT_1_0 = 0x0,
};

enum nvme_rdma_cm_status {
	NVME_RDMA_CM_INVALID_LEN	= 0x01,
	NVME_RDMA_CM_INVALID_RECFMT	= 0x02,
	NVME_RDMA_CM_INVALID_QID	= 0x03,
	NVME_RDMA_CM_INVALID_HSQSIZE	= 0x04,
	NVME_RDMA_CM_INVALID_HRQSIZE	= 0x05,
	NVME_RDMA_CM_NO_RSC		= 0x06,
	NVME_RDMA_CM_INVALID_IRD	= 0x07,
	NVME_RDMA_CM_INVALID_ORD	= 0x08,
	NVME_RDMA_CM_INVALID_CNTLID	= 0x09,
};

static inline const char *nvme_rdma_cm_msg(enum nvme_rdma_cm_status status)
{
	switch (status) {
	case NVME_RDMA_CM_INVALID_LEN:
		return "invalid length";
	case NVME_RDMA_CM_INVALID_RECFMT:
		return "invalid record format";
	case NVME_RDMA_CM_INVALID_QID:
		return "invalid queue ID";
	case NVME_RDMA_CM_INVALID_HSQSIZE:
		return "invalid host SQ size";
	case NVME_RDMA_CM_INVALID_HRQSIZE:
		return "invalid host RQ size";
	case NVME_RDMA_CM_NO_RSC:
		return "resource not found";
	case NVME_RDMA_CM_INVALID_IRD:
		return "invalid IRD";
	case NVME_RDMA_CM_INVALID_ORD:
		return "Invalid ORD";
	case NVME_RDMA_CM_INVALID_CNTLID:
		return "invalid controller ID";
	default:
		return "unrecognized reason";
	}
}

/**
 * struct nvme_rdma_cm_req - rdma connect request
 *
 * @recfmt:        format of the RDMA Private Data
 * @qid:           queue Identifier for the Admin or I/O Queue
 * @hrqsize:       host receive queue size to be created
 * @hsqsize:       host send queue size to be created
 */
struct nvme_rdma_cm_req {
	__le16		recfmt;
	__le16		qid;
	__le16		hrqsize;
	__le16		hsqsize;
	__le16		cntlid;
	u8		rsvd[22];
};

/**
 * struct nvme_rdma_cm_rep - rdma connect reply
 *
 * @recfmt:        format of the RDMA Private Data
 * @crqsize:       controller receive queue size
 */
struct nvme_rdma_cm_rep {
	__le16		recfmt;
	__le16		crqsize;
	u8		rsvd[28];
};

/**
 * struct nvme_rdma_cm_rej - rdma connect reject
 *
 * @recfmt:        format of the RDMA Private Data
 * @sts:           error status for the associated connect request
 */
struct nvme_rdma_cm_rej {
	__le16		recfmt;
	__le16		sts;
};

#endif /* _LINUX_NVME_RDMA_H */
     ˆ¿Ã„\iŸ¾ÂÅ -{    /* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2017-2018, Intel Corporation
 */

#ifndef __STRATIX10_SMC_H
#define __STRATIX10_SMC_H

#include <linux/arm-smccc.h>
#include <linux/bitops.h>

/**
 * This file defines the Secure Monitor Call (SMC) message protocol used for
 * service layer driver in normal world (EL1) to communicate with secure
 * monitor software in Secure Monitor Exception Level 3 (EL3).
 *
 * This file is shared with secure firmware (FW) which is out of kernel tree.
 *
 * An ARM SMC instruction takes a function identifier and up to 6 64-bit
 * register values as arguments, and can return up to 4 64-bit register
 * value. The operation of the secure monitor is determined by the parameter
 * values passed in through registers.
 *
 * EL1 and EL3 communicates pointer as physical address rather than the
 * virtual address.
 *
 * Functions specified by ARM SMC Calling convention:
 *
 * FAST call executes atomic operations, returns when the requested operation
 * has completed.
 * STD call starts a operation which can be preempted by a non-secure
 * interrupt. The call can return before the requested operation has
 * completed.
 *
 * a0..a7 is used as register names in the descriptions below, on arm32
 * that translates to r0..r7 and on arm64 to w0..w7.
 */

/**
 * @func_num: function ID
 */
#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
	ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
	ARM_SMCCC_OWNER_SIP, (func_num))

#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_S