MAJOR=7 MINOR=5 DEVNAME=vcs5 *l4( (  fB- | 7_I|+#U/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2017-2018 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H #define __DT_BINDINGS_CLOCK_IMX8MM_H #define IMX8MM_CLK_DUMMY 0 #define IMX8MM_CLK_32K 1 #define IMX8MM_CLK_24M 2 #define IMX8MM_OSC_HDMI_CLK 3 #define IMX8MM_CLK_EXT1 4 #define IMX8MM_CLK_EXT2 5 #define IMX8MM_CLK_EXT3 6 #define IMX8MM_CLK_EXT4 7 #define IMX8MM_AUDIO_PLL1_REF_SEL 8 #define IMX8MM_AUDIO_PLL2_REF_SEL 9 #define IMX8MM_VIDEO_PLL1_REF_SEL 10 #define IMX8MM_DRAM_PLL_REF_SEL 11 #define IMX8MM_GPU_PLL_REF_SEL 12 #define IMX8MM_VPU_PLL_REF_SEL 13 #define IMX8MM_ARM_PLL_REF_SEL 14 #define IMX8MM_SYS_PLL1_REF_SEL 15 #define IMX8MM_SYS_PLL2_REF_SEL 16 #define IMX8MM_SYS_PLL3_REF_SEL 17 #define IMX8MM_AUDIO_PLL1 18 #define IMX8MM_AUDIO_PLL2 19 #define IMX8MM_VIDEO_PLL1 20 #define IMX8MM_DRAM_PLL 21 #define IMX8MM_GPU_PLL 22 #define IMX8MM_VPU_PLL 23 #define IMX8MM_ARM_PLL 24 #define IMX8MM_SYS_PLL1 25 #define IMX8MM_SYS_PLL2 26 #define IMX8MM_SYS_PLL3 27 #define IMX8MM_AUDIO_PLL1_BYPASS 28 #define IMX8MM_AUDIO_PLL2_BYPASS 29 #define IMX8MM_VIDEO_PLL1_BYPASS 30 #define IMX8MM_DRAM_PLL_BYPASS 31 #define IMX8MM_GPU_PLL_BYPASS 32 #define IMX8MM_VPU_PLL_BYPASS 33 #define IMX8MM_ARM_PLL_BYPASS 34 #define IMX8MM_SYS_PLL1_BYPASS 35 #define IMX8MM_SYS_PLL2_BYPASS 36 #define IMX8MM_SYS_PLL3_BYPASS 37 #define IMX8MM_AUDIO_PLL1_OUT 38 #define IMX8MM_AUDIO_PLL2_OUT 39 #define IMX8MM_VIDEO_PLL1_OUT 40 #define IMX8MM_DRAM_PLL_OUT 41 #define IMX8MM_GPU_PLL_OUT 42 #define IMX8MM_VPU_PLL_OUT 43 #define IMX8MM_ARM_PLL_OUT 44 #define IMX8MM_SYS_PLL1_OUT 45 #define IMX8MM_SYS_PLL2_OUT 46 #define IMX8MM_SYS_PLL3_OUT 47 #define IMX8MM_SYS_PLL1_40M 48 #define IMX8MM_SYS_PLL1_80M 49 #define IMX8MM_SYS_PLL1_100M 50 #define IMX8MM_SYS_PLL1_133M 51 #define IMX8MM_SYS_PLL1_160M 52 #define IMX8MM_SYS_PLL1_200M 53 #define IMX8MM_SYS_PLL1_266M 54 #define IMX8MM_SYS_PLL1_400M 55 #define IMX8MM_SYS_PLL1_800M 56 #define IMX8MM_SYS_PLL2_50M 57 #define IMX8MM_SYS_PLL2_100M 58 #define IMX8MM_SYS_PLL2_125M 59 #define IMX8MM_SYS_PLL2_166M 60 #define IMX8MM_SYS_PLL2_200M 61 #define IMX8MM_SYS_PLL2_250M 62 #define IMX8MM_SYS_PLL2_333M 63 #define IMX8MM_SYS_PLL2_500M 64 #define IMX8MM_SYS_PLL2_1000M 65 /* core */ #define IMX8MM_CLK_A53_SRC 66 #define IMX8MM_CLK_M4_SRC 67 #define IMX8MM_CLK_VPU_SRC 68 #define IMX8MM_CLK_GPU3D_SRC 69 #define IMX8MM_CLK_GPU2D_SRC 70 #define IMX8MM_CLK_A53_CG 71 #define IMX8MM_CLK_M4_CG 72 #define IMX8MM_CLK_VPU_CG 73 #define IMX8MM_CLK_GPU3D_CG 74 #define IMX8MM_CLK_GPU2D_CG 75 #define IMX8MM_CLK_A53_DIV 76 #define IMX8MM_CLK_M4_DIV 77 #define IMX8MM_CLK_VPU_DIV 78 #define IMX8MM_CLK_GPU3D_DIV 79 #define IMX8MM_CLK_GPU2D_DIV 80 /* bus */ #define IMX8MM_CLK_MAIN_AXI 81 #define IMX8MM_CLK_ENET_AXI 82 #define IMX8MM_CLK_NAND_USDHC_BUS 83 #define IMX8MM_CLK_VPU_BUS 84 #define IMX8MM_CLK_DISP_AXI 85 #define IMX8MM_CLK_DISP_APB 86 #define IMX8MM_CLK_DISP_RTRM 87 #define IMX8MM_CLK_USB_BUS 88 #define IMX8MM_CLK_GPU_AXI 89 #define IMX8MM_CLK_GPU_AHB 90 #define IMX8MM_CLK_NOC 91 #define IMX8MM_CLK_NOC_APB 92 #define IMX8MM_CLK_AHB 93 #define IMX8MM_CLK_AUDIO_AHB 94 #define IMX8MM_CLK_IPG_ROOT 95 #define IMX8MM_CLK_IPG_AUDIO_ROOT 96 #define IMX8MM_CLK_DRAM_ALT 97 #define IMX8MM_CLK_DRAM_APB 98 #define IMX8MM_CLK_VPU_G1 99 #define IMX8MM_CLK_VPU_G2 100 #define IMX8MM_CLK_DISP_DTRC 101 #define IMX8MM_CLK_DISP_DC8000 102 #define IMX8MM_CLK_PCIE1_CTRL 103 #define IMX8MM_CLK_PCIE1_PHY 104 #define IMX8MM_CLK_PCIE1_AUX 105 #define IMX8MM_CLK_DC_PIXEL 106 #define IMX8MM_CLK_LCDIF_PIXEL 107 #define IMX8MM_CLK_SAI1 108 #define IMX8MM_CLK_SAI2 109 #define IMX8MM_CLK_SAI3 110 #define IMX8MM_CLK_SAI4 111 #define IMX8MM_CLK_SAI5 112 #define IMX8MM_CLK_SAI6 113 #define IMX8MM_CLK_SPDIF1 114 #define IMX8MM_CLK_SPD