MAJOR=4
MINOR=64
DEVNAME=ttyS0
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/*
 * Device Tree binding constants for HiSilicon Hi3670 SoC
 *
 * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
 * Copyright (c) 2018 Linaro Ltd.
 */

#ifndef __DT_BINDINGS_CLOCK_HI3670_H
#define __DT_BINDINGS_CLOCK_HI3670_H

/* clk in stub clock */
#define HI3670_CLK_STUB_CLUSTER0		0
#define HI3670_CLK_STUB_CLUSTER1		1
#define HI3670_CLK_STUB_GPU			2
#define HI3670_CLK_STUB_DDR			3
#define HI3670_CLK_STUB_DDR_VOTE		4
#define HI3670_CLK_STUB_DDR_LIMIT		5
#define HI3670_CLK_STUB_NUM			6

/* clk in crg clock */
#define HI3670_CLKIN_SYS			0
#define HI3670_CLKIN_REF			1
#define HI3670_CLK_FLL_SRC			2
#define HI3670_CLK_PPLL0			3
#define HI3670_CLK_PPLL1			4
#define HI3670_CLK_PPLL2			5
#define HI3670_CLK_PPLL3			6
#define HI3670_CLK_PPLL4			7
#define HI3670_CLK_PPLL6			8
#define HI3670_CLK_PPLL7			9
#define HI3670_CLK_PPLL_PCIE			10
#define HI3670_CLK_PCIEPLL_REV			11
#define HI3670_CLK_SCPLL			12
#define HI3670_PCLK				13
#define HI3670_CLK_UART0_DBG			14
#define HI3670_CLK_UART6			15
#define HI3670_OSC32K				16
#define HI3670_OSC19M				17
#define HI3670_CLK_480M				18
#define HI3670_CLK_INVALID			19
#define HI3670_CLK_DIV_SYSBUS			20
#define HI3670_CLK_FACTOR_MMC			21
#define HI3670_CLK_SD_SYS			22
#define HI3670_CLK_SDIO_SYS			23
#define HI3670_CLK_DIV_A53HPM			24
#define HI3670_CLK_DIV_320M			25
#define HI3670_PCLK_GATE_UART0			26
#define HI3670_CLK_FACTOR_UART0			27
#define HI3670_CLK_FACTOR_USB3PHY_PLL		28
#define HI3670_CLK_GATE_ABB_USB			29
#define HI3670_CLK_GATE_UFSPHY_REF		30
#define HI3670_ICS_VOLT_HIGH			31
#define HI3670_ICS_VOLT_MIDDLE			32
#define HI3670_VENC_VOLT_HOLD			33
#define HI3670_VDEC_VOLT_HOLD			34
#define HI3670_EDC_VOLT_HOLD			35
#define HI3670_CLK_ISP_SNCLK_FAC		36
#define HI3670_CLK_FACTOR_RXDPHY		37
#define HI3670_AUTODIV_SYSBUS			38
#define HI3670_AUTODIV_EMMC0BUS			39
#define HI3670_PCLK_ANDGT_MMC1_PCIE		40
#define HI3670_CLK_GATE_VCODECBUS_GT		41
#define HI3670_CLK_ANDGT_SD			42
#define HI3670_CLK_SD_SYS_GT			43
#define HI3670_CLK_ANDGT_SDIO			44
#define HI3670_CLK_SDIO_SYS_GT			45
#define HI3670_CLK_A53HPM_ANDGT			46
#define HI3670_CLK_320M_PLL_GT			47
#define HI3670_CLK_ANDGT_UARTH			48
#define HI3670_CLK_ANDGT_UARTL			49
#define HI3670_CLK_ANDGT_UART0			50
#define HI3670_CLK_ANDGT_SPI			51
#define HI3670_CLK_ANDGT_PCIEAXI		52
#define HI3670_CLK_DIV_AO_ASP_GT		53
#define HI3670_CLK_GATE_CSI_TRANS		54
#define HI3670_CLK_GATE_DSI_TRANS		55
#define HI3670_CLK_ANDGT_PTP			56
#define HI3670_CLK_ANDGT_OUT0			57
#define HI3670_CLK_ANDGT_OUT1			58
#define HI3670_CLKGT_DP_AUDIO_PLL_AO		59
#define HI3670_CLK_ANDGT_VDEC			60
#define HI3670_CLK_ANDGT_VENC			61
#define HI3670_CLK_ISP_SNCLK_ANGT		62
#define HI3670_CLK_ANDGT_RXDPHY			63
#define HI3670_CLK_ANDGT_ICS			64
#define HI3670_AUTODIV_DMABUS			65
#define HI3670_CLK_MUX_SYSBUS			66
#define HI3670_CLK_MUX_VCODECBUS		67
#define HI3670_CLK_MUX_SD_SYS			68
#define HI3670_CLK_MUX_SD_PLL			69
#define HI3670_CLK_MUX_SDIO_SYS			70
#define HI3670_CLK_MUX_SDIO_PLL			71
#define HI3670_CLK_MUX_A53HPM			72
#define HI3670_CLK_MUX_320M			73
#define HI3670_CLK_MUX_UARTH			74
#define HI3670_CLK_MUX_UARTL			75
#define HI3670_CLK_MUX_UART0			76
#define HI3670_CLK_MUX_I2C			77
#define HI3670_CLK_MUX_SPI			78
#define HI3670_CLK_MUX_PCIEAXI			79
#define HI3670_CLK_MUX_AO_ASP			80
#define HI3670_CLK_MUX_VDEC			81
#define HI3670_CLK_MUX_VENC			82
#define HI3670_CLK_ISP_SNCLK_MUX0		83
#define HI3670_CLK_ISP_SNCLK_MUX1		84
#define HI3670_CLK_ISP_SNCLK_MUX2		85
#define HI3670_CLK_MUX_RXDPHY_CFG		86
#define HI3670_CLK_MUX_ICS			87
#define HI3670_CLK_DIV_CFGBUS			88
#define HI3670_CLK_DIV_MMC0BUS			89
#define HI3670_CLK_DIV_MMC1BUS			90
#define HI3670_PCLK_DIV_MMC1_PCIE		91
#define HI3670_CLK_DIV_VCODECBUS		92
#define HI3670_CLK_DIV_SD			93
#define HI3670_CLK_DIV_SDIO			94
#define HI3670_CLK_DIV_UARTH			95
#define HI3670_CLK_DIV_UARTL			96
#define HI3670_CLK_DIV_UART0			97
#define 