MAJOR=4
MINOR=65
DEVNAME=ttyS1
      ˆl–ß=¿J	•2ÛB‚ œP@¸Ènå1hßÁ0À¿  *   ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿÂƒB_†I|¥�+ÂÁ Œ    /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright 2014 Ulrich Hecht
 */

#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
#define __DT_BINDINGS_CLOCK_R8A73A4_H__

/* CPG */
#define R8A73A4_CLK_MAIN	0
#define R8A73A4_CLK_PLL0	1
#define R8A73A4_CLK_PLL1	2
#define R8A73A4_CLK_PLL2	3
#define R8A73A4_CLK_PLL2S	4
#define R8A73A4_CLK_PLL2H	5
#define R8A73A4_CLK_Z		6
#define R8A73A4_CLK_Z2		7
#define R8A73A4_CLK_I		8
#define R8A73A4_CLK_M3		9
#define R8A73A4_CLK_B		10
#define R8A73A4_CLK_M1		11
#define R8A73A4_CLK_M2		12
#define R8A73A4_CLK_ZX		13
#define R8A73A4_CLK_ZS		14
#define R8A73A4_CLK_HP		15

/* MSTP2 */
#define R8A73A4_CLK_DMAC	18
#define R8A73A4_CLK_SCIFB3	17
#define R8A73A4_CLK_SCIFB2	16
#define R8A73A4_CLK_SCIFB1	7
#define R8A73A4_CLK_SCIFB0	6
#define R8A73A4_CLK_SCIFA0	4
#define R8A73A4_CLK_SCIFA1	3

/* MSTP3 */
#define R8A73A4_CLK_CMT1	29
#define R8A73A4_CLK_IIC1	23
#define R8A73A4_CLK_IIC0	18
#define R8A73A4_CLK_IIC7	17
#define R8A73A4_CLK_IIC6	16
#define R8A73A4_CLK_MMCIF0	15
#define R8A73A4_CLK_SDHI0	14
#define R8A73A4_CLK_SDHI1	13
#define R8A73A4_CLK_SDHI2	12
#define R8A73A4_CLK_MMCIF1	5
#define R8A73A4_CLK_IIC2	0

/* MSTP4 */
#define R8A73A4_CLK_IIC3	11
#define R8A73A4_CLK_IIC4	10
#define R8A73A4_CLK_IIC5	9
#define R8A73A4_CLK_INTC_SYS	8
#define R8A73A4_CLK_IRQC	7

/* MSTP5 */
#define R8A73A4_CLK_THERMAL	22
#define R8A73A4_CLK_IIC8	15

#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */
  .   ˆl–Ðz¾”jeJqAà[¸ÔÅ£Ä238_ŠI|¥�+õJi¿ÄÃ  î    @CONFIG@
log_selector =  +all
tls_require_ciphers = ALL:!ADH:RC4+RSA:+HIGH:+MEDIUM:-LOW:-SSLv2:-EXP
daemon_smtp_ports = 25: 26 : 465 : 587
disable_ipv6 = true
smtp_connect_backlog = 100
smtp_enforce_sync = true
smtp_receive_timeout = 30s
  "   	ˆl–Ü4ý( ©³( 	Å€fàD¦-ÿÆ465ÅÄ Ñ    	# SPDX-License-Identifier: GPL-2.0-only
menu "Broadcom SoC drivers"

config SOC_BRCMSTB
	bool "Broadcom STB SoC drivers"
	depends on ARM || ARM64 || BMIPS_GENERIC || COMPILE_TEST
	select SOC_BUS
	help
	  Enables drivers for the Broadcom Set-Top Box (STB) series of chips.
	  This option alone enables only some support code, while the drivers
	  can be enabled individually within this menu.

	  If unsure, say N.

source "drivers/soc/bcm/brcmstb/Kconfig"

endmenu
     ˆ¾Æ749ÅÄ í    # SPDX-License-Identifier: GPL-2.0-only
config WLAN_VENDOR_REALTEK
	bool "Realtek devices"
	default y
	help
	  If you have a wireless card belonging to this class, say Y.

	  Note that the answer to this question doesn't directly affect the
	  kernel: saying N will just cause the configurator to skip all the
	  questions about these cards. If you say Y, you will be asked for
	  your specific card in the following questions.

if WLAN_VENDOR_REALTEK

source "drivers/net/wireless/realtek/rtl818x/Kconfig"
source "drivers/net/wireless/realtek/rtlwifi/Kconfig"
source "drivers/net/wireless/realtek/rtl8xxxu/Kconfig"
source "drivers/net/wireless/realtek/rtw88/Kconfig"
source "drivers/net/wireless/realtek/rtw89/Kconfig"

endif # WLAN_VENDOR_REALTEK
     ˆÂÆƒm§ŸÁÅÄ q    /* SPDX-License-Identifier: GPL-2.0 */
#ifndef LINUX_SSB_PCICORE_H_
#define LINUX_SSB_PCICORE_H_

#include <linux/types.h>

struct pci_dev;


#ifdef CONFIG_SSB_DRIVER_PCICORE

/* PCI core registers. */
#define SSB_PCICORE_CTL			0x0000	/* PCI Control */
#define  SSB_PCICORE_CTL_RST_OE		0x00000001 /* PCI_RESET Output Enable */
#define  SSB_PCICORE_CTL_RST		0x00000002 /* PCI_RESET driven out to pin */
#define  SSB_PCICORE_CTL_CLK_OE		0x00000004 /* Clock gate Output Enable */
#define  SSB_PCICORE_CTL_CLK		0x00000008 /* Gate for clock driven out to pin */
#define SSB_PCICORE_ARBCTL		0x0010	/* PCI Arbiter Control */
#define  SSB_PCICORE_ARBCTL_INTERN	0x00000001 /* Use internal arbiter */
#define  SSB_PCICORE_ARBCTL_EXTERN	0x00000002 /* Use external arbiter */
#define  SSB_PCICORE_ARBCTL_PARKID	0x00000006 /* Mask, selects which agent is parked on an idle bus */
#define   SSB_PCICORE_ARBCTL_PARKID_LAST	0x0000000