auto ' 945_I|+'/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2020,2022 NXP */ #ifndef __PHY_LVDS_H_ #define __PHY_LVDS_H_ /** * struct phy_configure_opts_lvds - LVDS configuration set * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential * clock cycle. * @differential_clk_rate: Clock rate, in Hertz, of the LVDS * differential clock. * @lanes: Number of active, consecutive, * data lanes, starting from lane 0, * used for the transmissions. * @is_slave: Boolean, true if the phy is a slave * which works together with a master * phy to support dual link transmission, * otherwise a regular phy or a master phy. * * This structure is used to represent the configuration state of a LVDS phy. */ struct phy_configure_opts_lvds { unsigned int bits_per_lane_and_dclk_cycle; unsigned long differential_clk_rate; unsigned int lanes; bool is_slave; }; #endif /* __PHY_LVDS_H_ */ #)lY>T:fNi1h y]g?)0-,<4<8<d<e<g<z< <<< <<<=='=8=P=m="='=l=?>R>R?@@5E@/{@@@&@ @ A78ApAA2AAZAFLB1B$B,B%Ca=C>C3C*D=D!QDsD DDDBD)1E)[E*EE#E3E%F3AF%uF FFFFFG#8G%\GGG+GGG#H@HZHwHHHH#H I#I?I\IoI!III2IJ2*J%]JJK(KKK L&&LwML!LLnMM.M!M%MN1N0HNJyNN&N% O1OPHO$O(OOP!P59P,oP4P.P2QA3Q,uQEQ3QR(9R#bR4RR+RS #S DSQS"oS5S S6S$ T*/T,ZTTT'T,T-U%BU'hU>U U,U&VDVWV!pVVJV"V)W!EW-gW(WWW!WX X 6X@X PX#^XXX XX)XX Y"YR6YUYAYV!ZAxZ)Z<ZB![Gd[F[.[F"\8i\;\Z\]9]E]:]>^;W^-^7^^_/_"F_i__%__ __F_@`4R`4``Va;a;+b!gb0b bbbTc'hc!cc!cc2d4Ddyd-d3d dee-eHe feeeeeee f=fYfxfff%fNfFgegtggg*g:g% h*Fh$qh5h0h+h#)iMiaiBxi>i4i9/jvijj#k:$k$_kk.k'kkkl.l Hl UlIcl&lfl4;mFpm;m=m-1n_n-on,n5no!o2o&No)uoo=o)o' p 4pBp\pxpyp-q/q GqUq,hqq7qqr(r!Hrjr&rrr rr%s>sTsts|sHtOt0bt+t(tAt2*u]u=muuAu?v6Fv}v5v=v>wKBwQwMwW.xMxxx xMyUylyy+y(y