MAJOR=4 MINOR=58 DEVNAME=tty58  g  Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/class/tty/tty21/subsystem/tty39/power

Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/class/tty/tty21/subsystem/tty39/power

 NameLast modifiedSizeDescription
 Parent Directory   -  
 autosuspend_delay_ms 2026-10-12 08:45 4.0K 
 control 2026-10-12 08:45 4.0K 
 runtime_active_time 2026-10-12 08:45 4.0K 
 runtime_status 2026-10-12 08:45 4.0K 
 runtime_suspended_time 2026-10-12 08:45 4.0K 
  Index of /FSS-OZR/root/sys/dev/char/4:26/subsystem/tty19/power

Index of /FSS-OZR/root/sys/dev/char/4:26/subsystem/tty19/power

 NameLast modifiedSizeDescription
 Parent Directory   -  
 autosuspend_delay_ms 2026-10-12 08:39 4.0K 
 control 2026-10-12 08:39 4.0K 
 runtime_active_time 2026-10-12 08:39 4.0K 
 runtime_status 2026-10-12 08:39 4.0K 
 runtime_suspended_time 2026-10-12 08:39 4.0K 
*l4( (  fB- xN _I|+ F/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* * Copyright 2021 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H #define __DT_BINDINGS_CLOCK_IMX8ULP_H #define IMX8ULP_CLK_DUMMY 0 /* CGC1 */ #define IMX8ULP_CLK_SPLL2 5 #define IMX8ULP_CLK_SPLL3 6 #define IMX8ULP_CLK_A35_SEL 7 #define IMX8ULP_CLK_A35_DIV 8 #define IMX8ULP_CLK_SPLL2_PRE_SEL 9 #define IMX8ULP_CLK_SPLL3_PRE_SEL 10 #define IMX8ULP_CLK_SPLL3_PFD0 11 #define IMX8ULP_C