4 A l4( (  fB- _I|+am_J*j"Tv-ţX /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2025 Google Corporation */ #ifndef __HCI_DRV_H #define __HCI_DRV_H #include #include #include struct hci_drv_cmd_hdr { __le16 opcode; __le16 len; } __packed; struct hci_drv_ev_hdr { __le16 opcode; __le16 len; } __packed; #define HCI_DRV_EV_CMD_STATUS 0x0000 struct hci_drv_ev_cmd_status { __le16 opcode; __u8 status; } __packed; #define HCI_DRV_EV_CMD_COMPLETE 0x0001 struct hci_drv_ev_cmd_complete { __le16 opcode; __u8 status; __u8 data[]; } __packed; #define HCI_DRV_STATUS_SUCCESS 0x00 #define HCI_DRV_STATUS_UNSPECIFIED_ERROR 0x01 #define HCI_DRV_STATUS_UNKNOWN_COMMAND 0x02 #define HCI_DRV_STATUS_INVALID_PARAMETERS 0x03 #define HCI_DRV_MAX_DRIVER_NAME_LENGTH 32 /* Common commands that make sense on all drivers start from 0x0000 */ #define HCI_DRV_OP_READ_INFO 0x0000 #define HCI_DRV_READ_INFO_SIZE 0 struct hci_drv_rp_read_info { __u8 driver_name[HCI_DRV_MAX_DRIVER_NAME_LENGTH]; __le16 num_supported_commands; __le16 supported_commands[] __counted_by_le(num_supported_commands); } __packed; /* Driver specific OGF (Opcode Group Field) * Commands in this group may have different meanings across different drivers. */ #define HCI_DRV_OGF_DRIVER_SPECIFIC 0x01 int hci_drv_cmd_status(struct hci_dev *hdev, u16 cmd, u8 status); int hci_drv_cmd_complete(struct hci_dev *hdev, u16 cmd, u8 status, void *rp, size_t rp_len); int hci_drv_process_cmd(struct hci_dev *hdev, struct sk_buff *cmd_skb); struct hci_drv_handler { int (*func)(struct hci_dev *hdev, void *data, u16 data_len); size_t data_len; }; struct hci_drv { size_t common_handler_count; const struct hci_drv_handler *common_handlers; size_t specific_handler_count; const struct hci_drv_handler *specific_handlers; }; #endif /* __HCI_DRV_H */   m;' /* SPDX-License-Identifier: GPL-2.0 * * SuperH FLCTL nand controller * * Copyright © 2008 Renesas Solutions Corp. */ #ifndef __SH_FLCTL_H__ #define __SH_FLCTL_H__ #include #include #include #include #include /* FLCTL registers */ #define FLCMNCR(f) (f->reg + 0x0) #define FLCMDCR(f) (f->reg + 0x4) #define FLCMCDR(f) (f->reg + 0x8) #define FLADR(f) (f->reg + 0xC) #define FLADR2(f) (f->reg + 0x3C) #define FLDATAR(f) (f->reg + 0x10) #define FLDTCNTR(f) (f->reg + 0x14) #define FLINTDMACR(f) (f->reg + 0x18) #define FLBSYTMR(f) (f->reg + 0x1C) #define FLBSYCNT(f) (f->reg + 0x20) #define FLDTFIFO(f) (f->reg + 0x24) #define FLECFIFO(f) (f->reg + 0x28) #define FLTRCR(f) (f->reg + 0x2C) #define FLHOLDCR(f) (f->reg + 0x38) #define FL4ECCRESULT0(f) (f->reg + 0x80) #define FL4ECCRESULT1(f) (f->reg + 0x84) #define FL4ECCRESULT2(f) (f->reg + 0x88) #define FL4ECCRESULT3(f) (f->reg + 0x8C) #define FL4ECCCR(f) (f->reg + 0x90) #define FL4ECCCNT(f) (f->reg + 0x94) #define FLERRADR(f) (f->reg + 0x98) /* FLCMNCR control bits */ #define _4ECCCNTEN (0x1 << 24) #define _4ECCEN (0x1 << 23) #define _4ECCCORRECT (0x1 << 22) #define SHBUSSEL (0x1 << 20) #define SEL_16BIT (0x1 << 19) #define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/ #define QTSEL_E (0x1 << 17) #define ENDIAN (0x1 << 16) /* 1 = little endian */ #define FCKSEL_E (0x1 << 15) #define ACM_SACCES_MODE (0x01 << 10) #define NANWF_E (0x1 << 9) #define SE_D (0x1 << 8) /* Spare area disable */ #define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */ #define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */ #define TYPESEL_SET (0x1 << 0) /* * Clock settings using the PULSEx registers from FLCMNCR * * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E * to control the clock divider used between the High-Speed Peripheral Clock * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16 * bit versio