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  Index of /anon_sym/anon/proc/thread-self/root/lib/systemd/system/systemd-hostnamed.service.d

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* l4( (  fB- _I|+  /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved * * Declarations for Altera Arria10 MAX5 System Resource Chip * * Adapted from DA9052 */ #ifndef __MFD_ALTERA_A10SR_H #define __MFD_ALTERA_A10SR_H #include #include #include #include #include /* Write registers are always on even addresses */ #define WRITE_REG_MASK 0xFE /* Odd registers are always on odd addresses */ #define READ_REG_MASK 0x01 #define ALTR_A10SR_BITS_PER_REGISTER 8 /* * To find the correct register, we divide the input GPIO by * the number of GPIO in each register. We then need to multiply * by 2 because the reads are at odd addresses. */ #define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1) #define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER) #define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y)) #define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X)) /* Arria10 System Controller Register Defines */ #define ALTR_A10SR_NOP 0x00 /* No Change */ #define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */ #define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */ /* LED register Bit Definitions */ #define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */ #define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT #define ALTR_A10SR_OUT_VALID_RANGE_HI 7 #define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Inpu