in "lm_J*j"Tz. bѿ hauto  0"l4( (  fD- /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_SIGCONTEXT_H #define _ASM_X86_SIGCONTEXT_H /* This is a legacy header - all kernel code includes directly. */ #include #endif /* _ASM_X86_SIGCONTEXT_H */ ! am_J*j"Tzo\m1h Index of /anon_sym/anon/proc/self/root/usr/lib/firmware/cirrus/cs35l41/v6.61.1

Index of /anon_sym/anon/proc/self/root/usr/lib/firmware/cirrus/cs35l41/v6.61.1

 NameLast modifiedSizeDescription
 Parent Directory   -  
 halo_cspl_RAM_revB2_..>2026-05-19 08:39 17K 
"!lm_J*j"Tznm1h h!auto #_I|Mjq؂#File not found. % e %/* SPDX-License-Identifier: GPL-2.0-only */ /* * Header for the new SH dmaengine driver * * Copyright (C) 2010 Guennadi Liakhovetski */ #ifndef SH_DMA_H #define SH_DMA_H #include #include #include #include struct device; /* Used by slave DMA clients to request DMA to/from a specific peripheral */ struct sh_dmae_slave { struct shdma_slave shdma_slave; /* Set by the platform */ }; /* * Supplied by platforms to specify, how a DMA channel has to be configured for * a certain peripheral */ struct sh_dmae_slave_config { int slave_id; dma_addr_t addr; u32 chcr; char mid_rid; }; /** * struct sh_dmae_channel - DMAC channel platform data * @offset: register offset within the main IOMEM resource * @dmars: channel DMARS register offset * @chclr_offset: channel CHCLR register offset * @dmars_bit: channel DMARS field offset within the register * @chclr_bit: bit position, to be set to reset the channel */ struct sh_dmae_channel { unsigned int offset; unsigned int dmars; unsigned int chclr_offset; unsigned char dmars_bit; unsigned char chclr_bit; }; /** * struct sh_dmae_pdata - DMAC platform data * @slave: array of slaves * @slave_num: number of slaves in the above array * @channel: array of DMA channels * @channel_num: number of channels in the above array * @ts_low_shift: shift of the low part of the TS field * @ts_low_mask: low TS field mask * @ts_high_shift: additional shift of the high part of the TS field * @ts_high_mask: high TS field mask * @ts_shift: array of Transfer Size shifts, indexed by TS value * @ts_shift_num: number of shifts in the above array * @dmaor_init: DMAOR initialisation value * @chcr_offset: CHCR address offset * @chcr_ie_bit: CHCR Interrupt Enable bit * @dmaor_is_32bit: DMAOR is a 32-bit register * @needs_tend_set: the TEND register has to be set * @no_dmars: DMAC has no DMARS registers * @chclr_present: DMAC has one or several CHCLR registers * @chclr_bitwise: channel CHCLR registers are bitwise * @slave_only: DMAC cannot be used for MEMCPY */ struct sh_dmae_pdata { const struct sh_dmae_slave_config *slave; int slave_num; const struct sh_dmae_channel *channel; int channel_num; unsigned int ts_low_shift; unsigned int ts_low_mask; unsigned int ts_high_shift; unsigned int ts_high_mask; const unsigned int *ts_shift; int ts_shift_num; u16 dmaor_init; unsigned