pci:v00001AF4d00001000sv00001AF4sd00000001bc02sc00i00
  .   ˆl–Ãa¾”ªj"TÚ€Àã.)‹FÿÅ31_‹I|¥Žƒî4ÃVŸÂÄ      // Deprecated in WordPress 6.9.     �ÃÂÄ      File not found.
  +   ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿÇ„Bó?_†I|¥�+ÄÆ +¯    /* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Microsemi Switchtec PCIe Driver
 * Copyright (c) 2017, Microsemi Corporation
 */

#ifndef _SWITCHTEC_H
#define _SWITCHTEC_H

#include <linux/pci.h>
#include <linux/cdev.h>

#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
#define SWITCHTEC_MAX_PFF_CSR 255

#define SWITCHTEC_EVENT_OCCURRED BIT(0)
#define SWITCHTEC_EVENT_CLEAR    BIT(0)
#define SWITCHTEC_EVENT_EN_LOG   BIT(1)
#define SWITCHTEC_EVENT_EN_CLI   BIT(2)
#define SWITCHTEC_EVENT_EN_IRQ   BIT(3)
#define SWITCHTEC_EVENT_FATAL    BIT(4)
#define SWITCHTEC_EVENT_NOT_SUPP BIT(31)

#define SWITCHTEC_DMA_MRPC_EN	BIT(0)

#define MRPC_GAS_READ		0x29
#define MRPC_GAS_WRITE		0x87
#define MRPC_CMD_ID(x)		((x) & 0xffff)

enum {
	SWITCHTEC_GAS_MRPC_OFFSET       = 0x0000,
	SWITCHTEC_GAS_TOP_CFG_OFFSET    = 0x1000,
	SWITCHTEC_GAS_SW_EVENT_OFFSET   = 0x1800,
	SWITCHTEC_GAS_SYS_INFO_OFFSET   = 0x2000,
	SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
	SWITCHTEC_GAS_PART_CFG_OFFSET   = 0x4000,
	SWITCHTEC_GAS_NTB_OFFSET        = 0x10000,
	SWITCHTEC_GAS_PFF_CSR_OFFSET    = 0x134000,
};

enum switchtec_gen {
	SWITCHTEC_GEN3,
	SWITCHTEC_GEN4,
	SWITCHTEC_GEN5,
};

struct mrpc_regs {
	u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
	u32 cmd;
	u32 status;
	u32 ret_value;
	u32 dma_en;
	u64 dma_addr;
	u32 dma_vector;
	u32 dma_ver;
} __packed;

enum mrpc_status {
	SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
	SWITCHTEC_MRPC_STATUS_DONE = 2,
	SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
	SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
};

struct sw_event_regs {
	u64 event_report_ctrl;
	u64 reserved1;
	u64 part_event_bitmap;
	u64 reserved2;
	u32 global_summary;
	u32 reserved3[3];
	u32 stack_error_event_hdr;
	u32 stack_error_event_data;
	u32 reserved4[4];
	u32 ppu_error_event_hdr;
	u32 ppu_error_event_data;
	u32 reserved5[4];
	u32 isp_error_event_hdr;
	u32 isp_error_event_data;
	u32 reserved6[4];
	u32 sys_reset_event_hdr;
	u32 reserved7[5];
	u32 fw_exception_hdr;
	u32 reserved8[5];
	u32 fw_nmi_hdr;
	u32 reserved9[5];
	u32 fw_non_fatal_hdr;
	u32 reserved10[5];
	u32 fw_fatal_hdr;
	u32 reserved11[5];
	u32 twi_mrpc_comp_hdr;
	u32 twi_mrpc_comp_data;
	u32 reserved12[4];
	u32 twi_mrpc_comp_async_hdr;
	u32 twi_mrpc_comp_async_data;
	u32 reserved13[4];
	u32 cli_mrpc_comp_hdr;
	u32 cli_mrpc_comp_data;
	u32 reserved14[4];
	u32 cli_mrpc_comp_async_hdr;
	u32 cli_mrpc_comp_async_data;
	u32 reserved15[4];
	u32 gpio_interrupt_hdr;
	u32 gpio_interrupt_data;
	u32 reserved16[4];
	u32 gfms_event_hdr;
	u32 gfms_event_data;
	u32 reserved17[4];
} __packed;

enum {
	SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
	SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
	SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
	SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
};

enum {
	SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
	SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
	SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
	SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
	SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
	SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
	SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
	SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
	SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
	SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
};

enum {
	SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
	SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
	SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
	SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
	SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
	SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
	SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
	SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
};

struct sys_info_regs_gen3 {
	u32 reserved1;
	u32 vendor_table_revision;
	u32 table_format_version;
	u32 partition_id;
	u32 cfg_file_fmt_version;
	u16 cfg_running;
	u16 img_running;
	u32 reserved2[57];
	char vendor_id[8];
	char product_id[16];
	char product_revision[4];
	char component_vendor[8];
	u16 component_id;
	u8 component_revision;
} __packed;

struct sys_info_regs_gen4 {
	u16 gas_layout_ver;
	u8 evlist_ver;
	u8 reserved1;
	u16 mgmt_cmd_set_ver;
	u16 fabric