2576 *l4( (  fB- {_I|+/* SPDX-License-Identifier: GPL-2.0 */ /* * Definitions for PCI support. */ #define FL_BASE_MASK 0x0007 #define FL_BASE0 0x0000 #define FL_BASE1 0x0001 #define FL_BASE2 0x0002 #define FL_BASE3 0x0003 #define FL_BASE4 0x0004 #define FL_GET_BASE(x) (x & FL_BASE_MASK) /* Use successive BARs (PCI base address registers), else use offset into some specified BAR */ #define FL_BASE_BARS 0x0008 /* do not assign an irq */ #define FL_NOIRQ 0x0080 /* Use the Base address register size to cap number of ports */ #define FL_REGION_SZ_CAP 0x0100 struct pciserial_board { unsigned int flags; unsigned int num_ports; unsigned int base_baud; unsigned int uart_offset; unsigned int reg_shift; unsigned int first_offset; }; struct serial_private; struct serial_private * pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board); void pciserial_remove_ports(struct serial_private *priv); void pciserial_suspend_ports(struct serial_private *priv); void pciserial_resume_ports(struct serial_private *priv);  M_I|Mdv &K Index of /FSS-OZR/root/sys/dev/char/4:22/subsystem/tty10

Index of /FSS-OZR/root/sys/dev/char/4:22/subsystem/tty10

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 power/ 2026-10-10 20:12 -  
 subsystem/ 2026-10-10 14:31 -  
 qг9/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __LINUX_PARPORT_PC_H #define __LINUX_PARPORT_PC_H #include /* --- register definitions ------------------------------- */ #define ECONTROL(p) ((p)->base_hi + 0x2) #define CONFIGB(p) ((p)->base_hi + 0x1) #define CONFIGA(p) ((p)->base_hi + 0x0) #define FIFO(p) ((p)->base_hi + 0x0) #define EPPDATA(p) ((p)->base + 0x4) #define EPPADDR(p) ((p)->base + 0x3) #define CONTROL(p) ((p)->base + 0x2) #define STATUS(p) ((p)->base + 0x1) #define DATA(p) ((p)->base + 0x0) struct parport_pc_private { /* Contents of CTR. */ unsigned char ctr; /* Bitmask of writable CTR bits. */ unsigned char ctr_writable; /* Whether or not there's an ECR. */ int ecr; /* Number of PWords that FIFO will hold. */ int fifo_depth; /* Number of bytes per portword. */ int pword; /* Not used yet. */ int readIntrThreshold; int writeIntrThreshold; /* buffer suitable for DMA, if DMA enabled */ char *dma_buf; dma_addr_t dma_handle; struct list_head list; struct parport *port; }; struct parport_pc_via_data { /* ISA PnP IRQ routing register 1 */ u8 via_pci_parport_irq_reg; /* ISA PnP DMA request routing register */ u8 via_pci_parport_dma_reg; /* Register and value to enable SuperIO configuration access */ u8 via_pci_superio_config_reg; u8 via_pci_superio_config_data; /* SuperIO function register number */ u8 viacfg_function; /* parallel port control register