12 ˆÃÆ „ ï¶÷¿È?÷/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP */ #ifndef __DT_BINDINGS_RSCRC_IMX_H #define __DT_BINDINGS_RSCRC_IMX_H /* * These defines are used to indicate a resource. Resources include peripherals * and bus masters (but not memory regions). Note items from list should * never be changed or removed (only added to at the end of the list). */ #define IMX_SC_R_A53 0 #define IMX_SC_R_A53_0 1 #define IMX_SC_R_A53_1 2 #define IMX_SC_R_A53_2 3 #define IMX_SC_R_A53_3 4 #define IMX_SC_R_A72 5 #define IMX_SC_R_A72_0 6 #define IMX_SC_R_A72_1 7 #define IMX_SC_R_A72_2 8 #define IMX_SC_R_A72_3 9 #define IMX_SC_R_CCI 10 #define IMX_SC_R_DB 11 #define IMX_SC_R_DRC_0 12 #define IMX_SC_R_DRC_1 13 #define IMX_SC_R_GIC_SMMU 14 #define IMX_SC_R_IRQSTR_M4_0 15 #define IMX_SC_R_IRQSTR_M4_1 16 #define IMX_SC_R_SMMU 17 #define IMX_SC_R_GIC 18 #define IMX_SC_R_DC_0_BLIT0 19 #define IMX_SC_R_DC_0_BLIT1 20 #define IMX_SC_R_DC_0_BLIT2 21 #define IMX_SC_R_DC_0_BLIT_OUT 22 #define IMX_SC_R_PERF 23 #define IMX_SC_R_DC_0_WARP 25 #define IMX_SC_R_DC_0_VIDEO0 28 #define IMX_SC_R_DC_0_VIDEO1 29 #define IMX_SC_R_DC_0_FRAC0 30 #define IMX_SC_R_DC_0 32 #define IMX_SC_R_GPU_2_PID0 33 #define IMX_SC_R_DC_0_PLL_0 34 #define IMX_SC_R_DC_0_PLL_1 35 #define IMX_SC_R_DC_1_BLIT0 36 #define IMX_SC_R_DC_1_BLIT1 37 #define IMX_SC_R_DC_1_BLIT2 38 #define IMX_SC_R_DC_1_BLIT_OUT 39 #define IMX_SC_R_DC_1_WARP 42 #define IMX_SC_R_DC_1_VIDEO0 45 #define IMX_SC_R_DC_1_VIDEO1 46 #define IMX_SC_R_DC_1_FRAC0 47 #define IMX_SC_R_DC_1 49 #define IMX_SC_R_DC_1_PLL_0 51 #define IMX_SC_R_DC_1_PLL_1 52 #define IMX_SC_R_SPI_0 53 #define IMX_SC_R_SPI_1 54 #define IMX_SC_R_SPI_2 55 #define IMX_SC_R_SPI_3 56 #define IMX_SC_R_UART_0 57 #define IMX_SC_R_UART_1 58 #define IMX_SC_R_UART_2 59 #define IMX_SC_R_UART_3 60 #define IMX_SC_R_UART_4 61 #define IMX_SC_R_EMVSIM_0 62 #define IMX_SC_R_EMVSIM_1 63 #define IMX_SC_R_DMA_0_CH0 64 #define IMX_SC_R_DMA_0_CH1 65 #define IMX_SC_R_DMA_0_CH2 66 #define IMX_SC_R_DMA_0_CH3 67 #define IMX_SC_R_DMA_0_CH4 68 #define IMX_SC_R_DMA_0_CH5 69 #define IMX_SC_R_DMA_0_CH6 70 #define IMX_SC_R_DMA_0_CH7 71 #define IMX_SC_R_DMA_0_CH8 72 #define IMX_SC_R_DMA_0_CH9 73 #define IMX_SC_R_DMA_0_CH10 74 #define IMX_SC_R_DMA_0_CH11 75 #define IMX_SC_R_DMA_0_CH12 76 #define IMX_SC_R_DMA_0_CH13 77 #define IMX_SC_R_DMA_0_CH14 78 #define IMX_SC_R_DMA_0_CH15 79 #define IMX_SC_R_DMA_0_CH16 80 #define IMX_SC_R_DMA_0_CH17 81 #define IMX_SC_R_DMA_0_CH18 82 #define IMX_SC_R_DMA_0_CH19 83 #define IMX_SC_R_DMA_0_CH20 84 #define IMX_SC_R_DMA_0_CH21 85 #define IMX_SC_R_DMA_0_CH22 86 #define IMX_SC_R_DMA_0_CH23 87 #define IMX_SC_R_DMA_0_CH24 88 #define IMX_SC_R_DMA_0_CH25 89 #define IMX_SC_R_DMA_0_CH26 90 #define IMX_SC_R_DMA_0_CH27 91 #define IMX_SC_R_DMA_0_CH28 92 #define IMX_SC_R_DMA_0_CH29 93 #define IMX_SC_R_DMA_0_CH30 94 #define IMX_SC_R_DMA_0_CH31 95 #define IMX_SC_R_I2C_0 96 #define IMX_SC_R_I2C_1 97 #define IMX_SC_R_I2C_2 98 #define IMX_SC_R_I2C_3 99 #define IMX_SC_R_I2C_4 100 #define IMX_SC_R_ADC_0 101 #define IMX_SC_R_ADC_1 102 #define IMX_SC_R_FTM_0 103 #define IMX_SC_R_FTM_1 104 #define IMX_SC_R_CAN_0 105 #define IMX_SC_R_CAN_1 106 #define IMX_SC_R_CAN_2 107 #define IMX_SC_R_CAN(x) (IMX_SC_R_CAN_0 + (x)) #define IMX_SC_R_DMA_1_CH0 108 #define IMX_SC_R_DMA_1_CH1 109 #define IMX_SC_R_DMA_1_CH2 110 #define IMX_SC_R_DMA_1_CH3 111 #define IMX_SC_R_DMA_1_CH4 112 #define IMX_SC_R_DMA_1_CH5 113 #define IMX_SC_R_DMA_1_CH6 114 #define IMX_SC_R_DMA_1_CH7 115 #define IMX_SC_R_DMA_1_CH8 116 #define IMX_SC_R_DMA_1_CH9 117 #define IMX_SC_R_DMA_1_CH10 118 #define IMX_SC_R_DMA_1_CH11 119 #define IMX_SC_R_DMA_1_CH12 120 #define IMX_SC_R_DMA_1_CH13 121 #define IMX_SC_R_DMA_1_CH14 122 #define IMX_SC_R_DMA_1_CH15 123 #define IMX_SC_R_DMA_1_CH16 124 #define IMX_SC_R_DMA_1_CH17 125 #define IMX_SC_R_DMA_1_CH18 126 #define IM