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  B   €l–Ь4э( ©і( 	ЕЂfаB¦-яВ„ЂгЯ_†I|ҐЏ+a–Эm_J*j"Tв‚А†аD¦-яВ /$    /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 *
 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef QAIC_ACCEL_H_
#define QAIC_ACCEL_H_

#include "drm.h"

#if defined(__cplusplus)
extern "C" {
#endif

/* The length(4K) includes len and count fields of qaic_manage_msg */
#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K

/* semaphore flags */
#define QAIC_SEM_INSYNCFENCE	2
#define QAIC_SEM_OUTSYNCFENCE	1

/* Semaphore commands */
#define QAIC_SEM_NOP		0
#define QAIC_SEM_INIT		1
#define QAIC_SEM_INC		2
#define QAIC_SEM_DEC		3
#define QAIC_SEM_WAIT_EQUAL	4
#define QAIC_SEM_WAIT_GT_EQ	5 /* Greater than or equal */
#define QAIC_SEM_WAIT_GT_0	6 /* Greater than 0 */

#define QAIC_TRANS_UNDEFINED			0
#define QAIC_TRANS_PASSTHROUGH_FROM_USR		1
#define QAIC_TRANS_PASSTHROUGH_TO_USR		2
#define QAIC_TRANS_PASSTHROUGH_FROM_DEV		3
#define QAIC_TRANS_PASSTHROUGH_TO_DEV		4
#define QAIC_TRANS_DMA_XFER_FROM_USR		5
#define QAIC_TRANS_DMA_XFER_TO_DEV		6
#define QAIC_TRANS_ACTIVATE_FROM_USR		7
#define QAIC_TRANS_ACTIVATE_FROM_DEV		8
#define QAIC_TRANS_ACTIVATE_TO_DEV		9
#define QAIC_TRANS_DEACTIVATE_FROM_USR		10
#define QAIC_TRANS_DEACTIVATE_FROM_DEV		11
#define QAIC_TRANS_STATUS_FROM_USR		12
#define QAIC_TRANS_STATUS_TO_USR		13
#define QAIC_TRANS_STATUS_FROM_DEV		14
#define QAIC_TRANS_STATUS_TO_DEV		15
#define QAIC_TRANS_TERMINATE_FROM_DEV		16
#define QAIC_TRANS_TERMINATE_TO_DEV		17
#define QAIC_TRANS_DMA_XFER_CONT		18
#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV	19
#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV	20

/**
 * struct qaic_manage_trans_hdr - Header for a transaction in a manage message.
 * @type: In. Identifies this transaction. See QAIC_TRANS_* defines.
 * @len: In. Length of this transaction, including this header.
 */
struct qaic_manage_trans_hdr {
	__u32 type;
	__u32 len;
};

/**
 * struct qaic_manage_trans_passthrough - Defines a passthrough transaction.
 * @hdr: In. Header to identify this transaction.
 * @data: In. Payload of this transaction. Opaque to the driver. Userspace must
 *	  encode in little endian and align/pad to 64-bit.
 */
struct qaic_manage_trans_passthrough {
	struct qaic_manage_trans_hdr hdr;
	__u8 data[];
};

/**
 * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction.
 * @hdr: In. Header to identify this transaction.
 * @tag: In. Identified this transfer in other transactions. Opaque to the
 *	 driver.
 * @pad: Structure padding.
 * @addr: In. Address of the data to DMA to the device.
 * @size: In. Length of the data to DMA to the device.
 */
struct qaic_manage_trans_dma_xfer {
	struct qaic_manage_trans_hdr hdr;
	__u32 tag;
	__u32 pad;
	__u64 addr;
	__u64 size;
};

/**
 * struct qaic_manage_trans_activate_to_dev - Defines an activate request.
 * @hdr: In. Header to identify this transaction.
 * @queue_size: In. Number of elements for DBC request and response queues.
 * @eventfd: Unused.
 * @options: In. Device specific options for this activate.
 * @pad: Structure padding.  Must be 0.
 */
struct qaic_manage_trans_activate_to_dev {
	struct qaic_manage_trans_hdr hdr;
	__u32 queue_size;
	__u32 eventfd;
	__u32 options;
	__u32 pad;
};

/**
 * struct qaic_manage_trans_activate_from_dev - Defines an activate response.
 * @hdr: Out. Header to identify this transaction.
 * @status: Out. Return code of the request from the device.
 * @dbc_id: Out. Id of the assigned DBC for successful request.
 * @options: Out. Device specific options for this activate.
 */
struct qaic_manage_trans_activate_from_dev {
	struct qaic_manage_trans_hdr hdr;
	__u32 status;
	__u32 dbc_id;
	__u64 options;
};

/**
 * struct qaic_manage_trans_deactivate - Defines a deactivate request.
 * @hdr: In. Header to identify this transaction.
 * @dbc_id: In. Id of assigned DBC.
 * @pad: Structure padding.  Must be 0.
 */
struct qaic_manage_trans_deactivate {
	struct qaic_manage_trans_hdr hdr;
	__u32 dbc_id;
	__u32 pad;
};

/**
 *