1   o /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * I2C multiplexer using a single register * * Copyright 2015 Freescale Semiconductor * York Sun */ #ifndef __LINUX_PLATFORM_DATA_I2C_MUX_REG_H #define __LINUX_PLATFORM_DATA_I2C_MUX_REG_H /** * struct i2c_mux_reg_platform_data - Platform-dependent data for i2c-mux-reg * @parent: Parent I2C bus adapter number * @base_nr: Base I2C bus number to number adapters from or zero for dynamic * @values: Array of value for each channel * @n_values: Number of multiplexer channels * @little_endian: Indicating if the register is in little endian * @write_only: Reading the register is not allowed by hardware * @classes: Optional I2C auto-detection classes * @idle: Value to write to mux when idle * @idle_in_use: indicate if idle value is in use * @reg: Virtual address of the register to switch channel * @reg_size: register size in bytes */ struct i2c_mux_reg_platform_data { int parent; int base_nr; const unsigned int *values; int n_values; bool little_endian; bool write_only; const unsigned int *classes; u32 idle; bool idle_in_use; void __iomem *reg; resource_size_t reg_size; }; #endif /* __LINUX_PLATFORM_DATA_I2C_MUX_REG_H */ " li~ h8Eq1h 568 7zXZi"6!t/(kB YZ  287/* SPDX-License-Identifier: MIT */ /* * clock framework for AMD misc clocks * * Copyright 2018 Advanced Micro Devices, Inc. */ #ifndef __CLK_FCH_H #define __CLK_FCH_H #include struct fch_clk_data { void __iomem *base; char *name; }; #endif /* __CLK_FCH_H */  w+/* SPDX-License-Identifier: GPL-2.0-only */ /** * omap-twl4030.h - ASoC machine driver for TI SoC based boards with twl4030 * codec, header. * * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com * All rights reserved. * * Author: Peter Ujfalusi */ #ifndef _OMAP_TWL4030_H_ #define _OMAP_TWL4030_H_ /* To select if only one channel is connected in a stereo port */ #define OMAP_TWL4030_LEFT (1 << 0) #define OMAP_TWL4030_RIGHT (1 << 1) struct omap_tw4030_pdata { const char *card_name; /* Voice port is connected to McBSP3 */ bool voice_connected; /* The driver will parse the connection flags if this flag is set */ bool custom_routing; /* Flags to indicate connected audio ports. */ u8 has_hs; u8 has_hf; u8 has_predriv; u8 has_carkit; bool has_ear; bool has_mainmic; bool has_submic; bool has_hsmic; bool has_carkitmic; bool has_digimic0; bool has_digimic1; u8 has_linein; /* Jack detect GPIO or <= 0 if it is not implemented */ int jack_detect; }; #endif /* _OMAP_TWL4030_H_ */  465// SPDX-License-Identifier: GPL-2.0 /* * PLL clock driver for TI Davinci SoCs * * Copyright (C) 2018 David Lechner */ #ifndef __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ #define __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ #include /** * davinci_pll_platform_data * @cfgchip: CFGCHIP syscon regmap */ struct davinci_pll_platform_data { struct regmap *cfgchip; }; #endif /* __LINUX_PLATFORM_DATA_CLK_DAVINCI_PLL_H__ */  w Index of /anon_sym/anon/sys/module/nft_compat/sections

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