3  0+ h _I|+a4()P@ ~S?/* SPDX-License-Identifier: GPL-2.0 */ /* * Type definitions for the Microsoft hypervisor. */ #ifndef _HV_HVGDK_MINI_H #define _HV_HVGDK_MINI_H #include #include struct hv_u128 { u64 low_part; u64 high_part; } __packed; /* NOTE: when adding below, update hv_result_to_string() */ #define HV_STATUS_SUCCESS 0x0 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3 #define HV_STATUS_INVALID_ALIGNMENT 0x4 #define HV_STATUS_INVALID_PARAMETER 0x5 #define HV_STATUS_ACCESS_DENIED 0x6 #define HV_STATUS_INVALID_PARTITION_STATE 0x7 #define HV_STATUS_OPERATION_DENIED 0x8 #define HV_STATUS_UNKNOWN_PROPERTY 0x9 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA #define HV_STATUS_INSUFFICIENT_MEMORY 0xB #define HV_STATUS_INVALID_PARTITION_ID 0xD #define HV_STATUS_INVALID_VP_INDEX 0xE #define HV_STATUS_NOT_FOUND 0x10 #define HV_STATUS_INVALID_PORT_ID 0x11 #define HV_STATUS_INVALID_CONNECTION_ID 0x12 #define HV_STATUS_INSUFFICIENT_BUFFERS 0x13 #define HV_STATUS_NOT_ACKNOWLEDGED 0x14 #define HV_STATUS_INVALID_VP_STATE 0x15 #define HV_STATUS_NO_RESOURCES 0x1D #define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20 #define HV_STATUS_INVALID_LP_INDEX 0x41 #define HV_STATUS_INVALID_REGISTER_VALUE 0x50 #define HV_STATUS_OPERATION_FAILED 0x71 #define HV_STATUS_TIME_OUT 0x78 #define HV_STATUS_CALL_PENDING 0x79 #define HV_STATUS_VTL_ALREADY_ENABLED 0x86 /* * The Hyper-V TimeRefCount register and the TSC * page provide a guest VM clock with 100ns tick rate */ #define HV_CLOCK_HZ (NSEC_PER_SEC / 100) #define HV_HYP_PAGE_SHIFT 12 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) #define HV_HYP_LARGE_PAGE_SHIFT 21 #define HV_PARTITION_ID_INVALID ((u64)0) #define HV_PARTITION_ID_SELF ((u64)-1) /* Hyper-V specific model specific registers (MSRs) */ #if defined(CONFIG_X86) /* HV_X64_SYNTHETIC_MSR */ #define HV_X64_MSR_GUEST_OS_ID 0x40000000 #define HV_X64_MSR_HYPERCALL 0x40000001 #define HV_X64_MSR_VP_INDEX 0x40000002 #define HV_X64_MSR_RESET 0x40000003 #define HV_X64_MSR_VP_RUNTIME 0x40000010 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 /* Define the virtual APIC registers */ #define HV_X64_MSR_EOI 0x40000070 #define HV_X64_MSR_ICR 0x40000071 #define HV_X64_MSR_TPR 0x40000072 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 /* Define synthetic interrupt controller model specific registers. */ #define HV_X64_MSR_SCONTROL 0x40000080 #define HV_X64_MSR_SVERSION 0x40000081 #define HV_X64_MSR_SIEFP 0x40000082 #define HV_X64_MSR_SIMP 0x40000083 #define HV_X64_MSR_EOM 0x40000084 #define HV_X64_MSR_SIRBP 0x40000085 #define HV_X64_MSR_SINT0 0x40000090 #define HV_X64_MSR_SINT1 0x40000091 #define HV_X64_MSR_SINT2 0x40000092 #define HV_X64_MSR_SINT3 0x40000093 #define HV_X64_MSR_SINT4 0x40000094 #define HV_X64_MSR_SINT5 0x40000095 #define HV_X64_MSR_SINT6 0x40000096 #define HV_X64_MSR_SINT7 0x40000097 #define HV_X64_MSR_SINT8 0x40000098 #define HV_X64_MSR_SINT9 0x40000099 #define HV_X64_MSR_SINT10 0x4000009A #define HV_X64_MSR_SINT11 0x4000009B #define HV_X64_MSR_SINT12 0x4000009C #define HV_X64_MSR_SINT13 0x4000009D #define HV_X64_MSR_SINT14 0x4000009E #define HV_X64_MSR_SINT15 0x4000009F /* Define synthetic interrupt controller model specific registers for nested hypervisor */ #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 #define HV_X64_MSR_NESTED_SIMP 0x40001083 #define HV_X64_MSR_NESTED_EOM 0x40001084 #define HV_X64_MSR_NESTED_SINT0 0x40001090 /* * Synthetic Timer MSRs. Four timers per vcpu. */ #define HV_X64_MSR_STIMER