MAJOR=10 MINOR=125 DEVNAME=udmabuf *l4( (  fB- yE_I|+"/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Tomasz Figa * * Device Tree binding constants for Samsung Exynos3250 clock controllers. */ #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H /* * Let each exported clock get a unique index, which is used on DT-enabled * platforms to lookup the clock from a clock specifier. These indices are * therefore considered an ABI and so must not be changed. This implies * that new clocks should be added either in free spaces between clock groups * or at the end. */ /* * Main CMU */ #define CLK_OSCSEL 1 #define CLK_FIN_PLL 2 #define CLK_FOUT_APLL 3 #define CLK_FOUT_VPLL 4 #define CLK_FOUT_UPLL 5 #define CLK_FOUT_MPLL 6 #define CLK_ARM_CLK 7 /* Muxes */ #define CLK_MOUT_MPLL_USER_L 16 #define CLK_MOUT_GDL 17 #define CLK_MOUT_MPLL_USER_R 18 #define CLK_MOUT_GDR 19 #define CLK_MOUT_EBI 20 #define CLK_MOUT_ACLK_200 21 #define CLK_MOUT_ACLK_160 22 #define CLK_MOUT_ACLK_100 23 #define CLK_MOUT_ACLK_266_1 24 #define CLK_MOUT_ACLK_266_0 25 #define CLK_MOUT_ACLK_266 26 #define CLK_MOUT_VPLL 27 #define CLK_MOUT_EPLL_USER 28 #define CLK_MOUT_EBI_1 29 #define CLK_MOUT_UPLL 30 #define CLK_MOUT_ACLK_400_MCUISP_SUB 31 #define CLK_MOUT_MPLL 32 #define CLK_MOUT_ACLK_400_MCUISP 33 #define CLK_MOUT_VPLLSRC 34 #define CLK_MOUT_CAM1 35 #define CLK_MOUT_CAM_BLK 36 #define CLK_MOUT_MFC 37 #define CLK_MOUT_MFC_1 38 #define CLK_MOUT_MFC_0 39 #define CLK_MOUT_G3D 40 #define CLK_MOUT_G3D_1 41 #define CLK_MOUT_G3D_0 42 #define CLK_MOUT_MIPI0 43 #define CLK_MOUT_FIMD0 44 #define CLK_MOUT_UART_ISP 45 #define CLK_MOUT_SPI1_ISP 46 #define CLK_MOUT_SPI0_ISP 47 #define CLK_MOUT_TSADC 48 #define CLK_MOUT_MMC1 49 #define CLK_MOUT_MMC0 50 #define CLK_MOUT_UART1 51 #define CLK_MOUT_UART0 52 #define CLK_MOUT_SPI1 53 #define CLK_MOUT_SPI0 54 #define CLK_MOUT_AUDIO 55 #define CLK_MOUT_MPLL_USER_C 56 #define CLK_MOUT_HPM 57 #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 #define CLK_MOUT_UART2 61 #define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 #define CLK_DIV_GDL 65 #define CLK_DIV_GPR 66 #define CLK_DIV_GDR 67 #define CLK_DIV_MPLL_PRE 68 #define CLK_DIV_ACLK_400_MCUISP 69 #define CLK_DIV_EBI 70 #define CLK_DIV_ACLK_200 71 #define CLK_DIV_ACLK_160 72 #define CLK_DIV_ACLK_100 73 #define CLK_DIV_ACLK_266 74 #define CLK_DIV_CAM1 75 #define CLK_DIV_CAM_BLK 76 #define CLK_DIV_MFC 77 #define CLK_DIV_G3D 78 #define CLK_DIV_MIPI0_PRE 79 #define CLK_DIV_MIPI0 80 #define CLK_DIV_FIMD0 81 #define CLK_DIV_UART_ISP 82 #define CLK_DIV_SPI1_ISP_PRE 83 #define CLK_DIV_SPI1_ISP 84 #define CLK_DIV_SPI0_ISP_PRE 85 #define CLK_DIV_SPI0_ISP 86 #define CLK_DIV_TSADC_PRE 87 #define CLK_DIV_TSADC 88 #define CLK_DIV_MMC1_PRE 89 #define CLK_DIV_MMC1 90 #define CLK_DIV_MMC0_PRE 91 #define CLK_DIV_MMC0 92 #define CLK_DIV_UART1 93 #define CLK_DIV_UART0 94 #define CLK_DIV_SPI1_PRE 95 #define CLK_DIV_SPI1 96 #define CLK_DIV_SPI0_PRE 97 #define CLK_DIV_SPI0 98 #define CLK_DIV_PCM 99 #define CLK_DIV_AUDIO 100 #define CLK_DIV_I2S 101 #define CLK_DIV_CORE2 102 #define CLK_DIV_APLL 103 #define CLK_DIV_PCLK_DBG 104 #define CLK_DIV_ATB 105 #define CLK_DIV_COREM 106 #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 #define CLK_DIV_UART2 110 #define CLK_DIV_MMC2_PRE 111 #define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 #define CLK_ASYNC_MFCL 129 #define CLK_PPMULEFT 130 #define CLK_GPIO_LEFT 131 #define CLK_ASYNC_ISPMX 132 #define CLK_ASYNC_FSYSD 133 #define CLK_ASYNC_LCD0X 134 #define CLK_ASYNC_CAMX 135 #define CLK_PPMURIGHT 136 #define CLK_GPIO_RIGHT 137 #define CLK_MONOCNT 138 #define CLK_TZPC6 139 #define CLK_PROVISIONKEY1 140 #define CLK_PR