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936 #/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef _LINUX_IN_ROUTE_H
#define _LINUX_IN_ROUTE_H
/* IPv4 routing cache flags */
#define RTCF_DEAD RTNH_F_DEAD
#define RTCF_ONLINK RTNH_F_ONLINK
/* Obsolete flag. About to be deleted */
#define RTCF_NOPMTUDISC RTM_F_NOPMTUDISC
#define RTCF_NOTIFY 0x00010000
#define RTCF_DIRECTDST 0x00020000 /* unused */
#define RTCF_REDIRECTED 0x00040000
#define RTCF_TPROXY 0x00080000 /* unused */
#define RTCF_FAST 0x00200000 /* unused */
#define RTCF_MASQ 0x00400000 /* unused */
#define RTCF_SNAT 0x00800000 /* unused */
#define RTCF_DOREDIRECT 0x01000000
#define RTCF_DIRECTSRC 0x04000000
#define RTCF_DNAT 0x08000000
#define RTCF_BROADCAST 0x10000000
#define RTCF_MULTICAST 0x20000000
#define RTCF_REJECT 0x40000000 /* unused */
#define RTCF_LOCAL 0x80000000
#define RTCF_NAT (RTCF_DNAT|RTCF_SNAT)
#define RT_TOS(tos) ((tos)&IPTOS_TOS_MASK)
#endif /* _LINUX_IN_ROUTE_H */
%
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Index of /FSS-OZR/root/sys/dev/char/4:18/subsystem/tty49
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xN F +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
* Copyright 2021 NXP
*/
#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
#define __DT_BINDINGS_CLOCK_IMX8ULP_H
#define IMX8ULP_CLK_DUMMY 0
/* CGC1 */
#define IMX8ULP_CLK_SPLL2 5
#define IMX8ULP_CLK_SPLL3 6
#define IMX8ULP_CLK_A35_SEL 7
#define IMX8ULP_CLK_A35_DIV 8
#define IMX8ULP_CLK_SPLL2_PRE_SEL 9
#define IMX8ULP_CLK_SPLL3_PRE_SEL 10
#define IMX8ULP_CLK_SPLL3_PFD0 11
#define IMX8ULP_CLK_SPLL3_PFD1 12
#define IMX8ULP_CLK_SPLL3_PFD2 13
#define IMX8ULP_CLK_SPLL3_PFD3 14
#define IMX8ULP_CLK_SPLL3_PFD0_DIV1 15
#define IMX8ULP_CLK_SPLL3_PFD0_DIV2 16
#define IMX8ULP_CLK_SPLL3_PFD1_DIV1 17
#define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18
#define IMX8ULP_CLK_SPLL3_PFD2_DIV1 19
#define IMX8ULP_CLK_SPLL3_PFD2_DIV2 20
#define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21
#define IMX8ULP_CLK_SPLL3_PFD3_DIV2 22
#define IMX8ULP_CLK_NIC_SEL 23
#define IMX8ULP_CLK_NIC_AD_DIVPLAT 24
#define IMX8ULP_CLK_NIC_PER_DIVPLAT 25
#define IMX8ULP_CLK_XBAR_SEL 26
#define IMX8ULP_CLK_XBAR_AD_DIVPLAT 27
#define IMX8ULP_CLK_XBAR_DIVBUS 28
#define IMX8ULP_CLK_XBAR_AD_SLOW 29
#define IMX8ULP_CLK_SOSC_DIV1 30
#define IMX8ULP_CLK_SOSC_DIV2 31
#define IMX8ULP_CLK_SOSC_DIV3 32
#define IMX8ULP_CLK_FROSC_DIV1 33
#define IMX8ULP_CLK_FROSC_DIV2 34
#define IMX8ULP_CLK_FROSC_DIV3 35
#define IMX8ULP_CLK_SPLL3_VCODIV 36
#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE 37
#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE 38
#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE 39
#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE 40
#define IMX