suspended ˆÃ ƒqñ?ÁÀ¿/* SPDX-License-Identifier: GPL-2.0 */ #ifndef LINUX_BCMA_DRIVER_PCIE2_H_ #define LINUX_BCMA_DRIVER_PCIE2_H_ #define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000 #define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */ #define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */ #define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */ #define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010 #define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */ #define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */ #define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */ #define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004 #define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008 #define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C #define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010 #define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014 #define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018 #define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C #define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020 #define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100 #define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104 #define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108 #define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C #define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120 #define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124 #define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128 #define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C #define BCMA_CORE_PCIE2_MDIORDDATA 0x0130 #define BCMA_CORE_PCIE2_DATAINTF 0x0180 #define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188 #define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c #define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190 #define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194 #define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198 #define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c #define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */ #define PCIE2_LTR_ACTIVE 2 #define PCIE2_LTR_ACTIVE_IDLE 1 #define PCIE2_LTR_SLEEP 0 #define PCIE2_LTR_FINAL_MASK 0x300 #define PCIE2_LTR_FINAL_SHIFT 8 #define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4 #define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8 #define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8 #define BCMA_CORE_PCIE2_CFG_DATA 0x01FC #define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200 #define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204 #define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208 #define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210 #define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214 #define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218 #define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C #define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220 #define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224 #define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250 #define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254 #define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258 #define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C #define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260 #define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264 #define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268 #define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C #define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270 #define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274 #define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278 #define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C #define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330 #define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334 #define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340 #define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344 #define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348 #define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350 #define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354 #define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358 #define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C #define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360 #define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364 #define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370 #define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374 #define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) #define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00 #define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04 #define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08 #define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C #define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10 #define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14 #define BCMA_CORE_PCIE2_FUNC0