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  	   !ˆÀÆ0¾Ä     #ˆÀÆƒxN_†I|¥�+¿Å  F    #/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
 * Copyright 2021 NXP
 */

#ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
#define __DT_BINDINGS_CLOCK_IMX8ULP_H

#define IMX8ULP_CLK_DUMMY			0

/* CGC1 */
#define IMX8ULP_CLK_SPLL2			5
#define IMX8ULP_CLK_SPLL3			6
#define IMX8ULP_CLK_A35_SEL			7
#define IMX8ULP_CLK_A35_DIV			8
#define IMX8ULP_CLK_SPLL2_PRE_SEL		9
#define IMX8ULP_CLK_SPLL3_PRE_SEL		10
#define IMX8ULP_CLK_SPLL3_PFD0			11
#define IMX8ULP_CLK_SPLL3_PFD1			12
#define IMX8ULP_CLK_SPLL3_PFD2			13
#define IMX8ULP_CLK_SPLL3_PFD3			14
#define IMX8ULP_CLK_SPLL3_PFD0_DIV1		15
#define IMX8ULP_CLK_SPLL3_PFD0_DIV2		16
#define IMX8ULP_CLK_SPLL3_PFD1_DIV1		17
#define IMX8ULP_CLK_SPLL3_PFD1_DIV2		18
#define IMX8ULP_CLK_SPLL3_PFD2_DIV1		19
#define IMX8ULP_CLK_SPLL3_PFD2_DIV2		20
#define IMX8ULP_CLK_SPLL3_PFD3_DIV1		21
#define IMX8ULP_CLK_SPLL3_PFD3_DIV2		22
#define IMX8ULP_CLK_NIC_SEL			23
#define IMX8ULP_CLK_NIC_AD_DIVPLAT		24
#define IMX8ULP_CLK_NIC_PER_DIVPLAT		25
#define IMX8ULP_CLK_XBAR_SEL			26
#define IMX8ULP_CLK_XBAR_AD_DIVPLAT		27
#define IMX8ULP_CLK_XBAR_DIVBUS			28
#define IMX8ULP_CLK_XBAR_AD_SLOW		29
#define IMX8ULP_CLK_SOSC_DIV1			30
#define IMX8ULP_CLK_SOSC_DIV2			31
#define IMX8ULP_CLK_SOSC_DIV3			32
#define IMX8ULP_CLK_FROSC_DIV1			33
#define IMX8ULP_CLK_FROSC_DIV2			34
#define IMX8ULP_CLK_FROSC_DIV3			35
#define IMX8ULP_CLK_SPLL3_VCODIV		36
#define IMX8ULP_CLK_SPLL3_PFD0_DIV1_GATE	37
#define IMX8ULP_CLK_SPLL3_PFD0_DIV2_GATE	38
#define IMX8ULP_CLK_SPLL3_PFD1_DIV1_GATE	39
#define IMX8ULP_CLK_SPLL3_PFD1_DIV2_GATE	40
#define IMX8ULP_CLK_SPLL3_PFD2_DIV1_GATE	41
#define IMX8ULP_CLK_SPLL3_PFD2_DIV2_GATE	42
#define IMX8ULP_CLK_SPLL3_PFD3_DIV1_GATE	43
#define IMX8ULP_CLK_SPLL3_PFD3_DIV2_GATE	44
#define IMX8ULP_CLK_SOSC_DIV1_GATE		45
#define IMX8ULP_CLK_SOSC_DIV2_GATE		46
#define IMX8ULP_CLK_SOSC_DIV3_GATE		47
#define IMX8ULP_CLK_FROSC_DIV1_GATE		48
#define IMX8ULP_CLK_FROSC_DIV2_GATE		49
#define IMX8ULP_CLK_FROSC_DIV3_GATE		50
#define IMX8ULP_CLK_SAI4_SEL			51
#define IMX8ULP_CLK_SAI5_SEL			52
#define IMX8ULP_CLK_AUD_CLK1			53
#define IMX8ULP_CLK_ARM				54
#define IMX8ULP_CLK_ENET_TS_SEL			55

#define IMX8ULP_CLK_CGC1_END			56

/* CGC2 */
#define IMX8ULP_CLK_PLL4_PRE_SEL	0
#define IMX8ULP_CLK_PLL4		1
#define IMX8ULP_CLK_PLL4_VCODIV		2
#define IMX8ULP_CLK_DDR_SEL		3
#define IMX8ULP_CLK_DDR_DIV		4
#define IMX8ULP_CLK_LPAV_AXI_SEL	5
#define IMX8ULP_CLK_LPAV_AXI_DIV	6
#define IMX8ULP_CLK_LPAV_AHB_DIV	7
#define IMX8ULP_CLK_LPAV_BUS_DIV	8
#define IMX8ULP_CLK_PLL4_PFD0		9
#define IMX8ULP_CLK_PLL4_PFD1		10
#define IMX8ULP_CLK_PLL4_PFD2		11
#define IMX8ULP_CLK_PLL4_PFD3		12
#define IMX8ULP_CLK_PLL4_PFD0_DIV1_GATE	13
#define IMX8ULP_CLK_PLL4_PFD0_DIV2_GATE	14
#define IMX8ULP_CLK_PLL4_PFD1_DIV1_GATE	15
#define IMX8ULP_CLK_PLL4_PFD1_DIV2_GATE	16
#define IMX8ULP_CLK_PLL4_PFD2_DIV1_GATE	17
#define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE	18
#define IMX8ULP_CLK_PLL4_PFD3_DIV1_GATE	19
#define IMX8ULP_CLK_PLL4_PFD3_DIV2_GATE	20
#define IMX8ULP_CLK_PLL4_PFD0_DIV1	21
#define IMX8ULP_CLK_PLL4_PFD0_DIV2	22
#define IMX8ULP_CLK_PLL4_PFD1_DIV1	23
#define IMX8ULP_CLK_PLL4_PFD1_DIV2	24
#define IMX8ULP_CLK_PLL4_PFD2_DIV1	25
#define IMX8ULP_CLK_PLL4_PFD2_DIV2	26
#define IMX8ULP_CLK_PLL4_PFD3_DIV1	27
#define IMX8ULP_CLK_PLL4_PFD3_DIV2	28
#define IMX8ULP_CLK_CGC2_SOSC_DIV1_GATE	29
#define IMX8ULP_CLK_CGC2_SOSC_DIV2_GATE	30
#define IMX8ULP_CLK_CGC2_SOSC_DIV3_GATE	31
#define IMX8ULP_CLK_CGC2_SOSC_DIV1	32
#define IMX8ULP_CLK_CGC2_SOSC_DIV2	33
#define IMX8ULP_CLK_CGC2_SOSC_DIV3	34
#define IMX8ULP_CLK_CGC2_FROSC_DIV1_GATE	35
#define IMX8ULP_CLK_CGC2_FROSC_DIV2_GATE	36
#define IMX8ULP_CLK_CGC2_FROSC_DIV3_GATE	37
#define IMX8ULP_CLK_CGC2_FROSC_DIV1	38
#define IMX8ULP_CLK_CGC2_FROSC_DIV2	39
#define IMX8ULP_CLK_CGC2_FROSC_DIV3	40
#define IMX8ULP_CLK_AUD_CLK2		41
#define IMX8ULP_CLK_SAI6_SEL		42
#define IMX8ULP_CLK_SAI7_SEL		43
#define IMX8ULP_CLK_SPDIF_SEL		44
#define IMX8ULP_CLK_HIFI_SEL		45
#define IMX8ULP_CLK_HIFI_DIVCORE	46
#define IMX8ULP_CLK_HIFI_DIVPLAT	47
#define IMX8ULP_CLK_DSI_PHY_REF		48

#define I