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     5ˆÉÍ„nïÀ¿Ë <ø    5/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright 2021 ROHM Semiconductors.
 *
 * Author: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
 *
 * Copyright 2014 Embest Technology Co. Ltd. Inc.
 *
 * Author: yanglsh@embest-tech.com
 */

#ifndef _MFD_BD71815_H
#define _MFD_BD71815_H

#include <linux/regmap.h>

enum {
	BD71815_BUCK1	=	0,
	BD71815_BUCK2,
	BD71815_BUCK3,
	BD71815_BUCK4,
	BD71815_BUCK5,
	/* General Purpose */
	BD71815_LDO1,
	BD71815_LDO2,
	BD71815_LDO3,
	/* LDOs for SD Card and SD Card Interface */
	BD71815_LDO4,
	BD71815_LDO5,
	/* LDO for DDR Reference Voltage */
	BD71815_LDODVREF,
	/* LDO for Low-Power State Retention */
	BD71815_LDOLPSR,
	BD71815_WLED,
	BD71815_REGULATOR_CNT,
};

#define BD71815_SUPPLY_STATE_ENABLED    0x1

enum {
	BD71815_REG_DEVICE		= 0,
	BD71815_REG_PWRCTRL,
	BD71815_REG_BUCK1_MODE,
	BD71815_REG_BUCK2_MODE,
	BD71815_REG_BUCK3_MODE,
	BD71815_REG_BUCK4_MODE,
	BD71815_REG_BUCK5_MODE,
	BD71815_REG_BUCK1_VOLT_H,
	BD71815_REG_BUCK1_VOLT_L,
	BD71815_REG_BUCK2_VOLT_H,
	BD71815_REG_BUCK2_VOLT_L,
	BD71815_REG_BUCK3_VOLT,
	BD71815_REG_BUCK4_VOLT,
	BD71815_REG_BUCK5_VOLT,
	BD71815_REG_LED_CTRL,
	BD71815_REG_LED_DIMM,
	BD71815_REG_LDO_MODE1,
	BD71815_REG_LDO_MODE2,
	BD71815_REG_LDO_MODE3,
	BD71815_REG_LDO_MODE4,
	BD71815_REG_LDO1_VOLT,
	BD71815_REG_LDO2_VOLT,
	BD71815_REG_LDO3_VOLT,
	BD71815_REG_LDO4_VOLT,
	BD71815_REG_LDO5_VOLT_H,
	BD71815_REG_LDO5_VOLT_L,
	BD71815_REG_BUCK_PD_DIS,
	BD71815_REG_LDO_PD_DIS,
	BD71815_REG_GPO,
	BD71815_REG_OUT32K,
	BD71815_REG_SEC,
	BD71815_REG_MIN,
	BD71815_REG_HOUR,
	BD71815_REG_WEEK,
	BD71815_REG_DAY,
	BD71815_REG_MONTH,
	BD71815_REG_YEAR,
	BD71815_REG_ALM0_SEC,

	BD71815_REG_ALM1_SEC		= 0x2C,

	BD71815_REG_ALM0_MASK		= 0x33,
	BD71815_REG_ALM1_MASK,
	BD71815_REG_ALM2,
	BD71815_REG_TRIM,
	BD71815_REG_CONF,
	BD71815_REG_SYS_INIT,
	BD71815_REG_CHG_STATE,
	BD71815_REG_CHG_LAST_STATE,
	BD71815_REG_BAT_STAT,
	BD71815_REG_DCIN_STAT,
	BD71815_REG_VSYS_STAT,
	BD71815_REG_CHG_STAT,
	BD71815_REG_CHG_WDT_STAT,
	BD71815_REG_BAT_TEMP,
	BD71815_REG_IGNORE_0,
	BD71815_REG_INHIBIT_0,
	BD71815_REG_DCIN_CLPS,
	BD71815_REG_VSYS_REG,
	BD71815_REG_VSYS_MAX,
	BD71815_REG_VSYS_MIN,
	BD71815_REG_CHG_SET1,
	BD71815_REG_CHG_SET2,
	BD71815_REG_CHG_WDT_PRE,
	BD71815_REG_CHG_WDT_FST,
	BD71815_REG_CHG_IPRE,
	BD71815_REG_CHG_IFST,
	BD71815_REG_CHG_IFST_TERM,
	BD71815_REG_CHG_VPRE,
	BD71815_REG_CHG_VBAT_1,
	BD71815_REG_CHG_VBAT_2,
	BD71815_REG_CHG_VBAT_3,
	BD71815_REG_CHG_LED_1,
	BD71815_REG_VF_TH,
	BD71815_REG_BAT_SET_1,
	BD71815_REG_BAT_SET_2,
	BD71815_REG_BAT_SET_3,
	BD71815_REG_ALM_VBAT_TH_U,
	BD71815_REG_ALM_VBAT_TH_L,
	BD71815_REG_ALM_DCIN_TH,
	BD71815_REG_ALM_VSYS_TH,
	BD71815_REG_VM_IBAT_U,
	BD71815_REG_VM_IBAT_L,
	BD71815_REG_VM_VBAT_U,
	BD71815_REG_VM_VBAT_L,
	BD71815_REG_VM_BTMP,
	BD71815_REG_VM_VTH,
	BD71815_REG_VM_DCIN_U,
	BD71815_REG_VM_DCIN_L,
	BD71815_REG_VM_VSYS,
	BD71815_REG_VM_VF,
	BD71815_REG_VM_OCI_PRE_U,
	BD71815_REG_VM_OCI_PRE_L,
	BD71815_REG_VM_OCV_PRE_U,
	BD71815_REG_VM_OCV_PRE_L,
	BD71815_REG_VM_OCI_PST_U,
	BD71815_REG_VM_OCI_PST_L,
	BD71815_REG_VM_OCV_PST_U,
	BD71815_REG_VM_OCV_PST_L,
	BD71815_REG_VM_SA_VBAT_U,
	BD71815_REG_VM_SA_VBAT_L,
	BD71815_REG_VM_SA_IBAT_U,
	BD71815_REG_VM_SA_IBAT_L,
	BD71815_REG_CC_CTRL,
	BD71815_REG_CC_BATCAP1_TH_U,
	BD71815_REG_CC_BATCAP1_TH_L,
	BD71815_REG_CC_BATCAP2_TH_U,
	BD71815_REG_CC_BATCAP2_TH_L,
	BD71815_REG_CC_BATCAP3_TH_U,
	BD71815_REG_CC_BATCAP3_TH_L,
	BD71815_REG_CC_STAT,
	BD71815_REG_CC_CCNTD_3,
	BD71815_REG_CC_CCNTD_2,
	BD71815_REG_CC_CCNTD_1,
	BD71815_REG_CC_CCNTD_0,
	BD71815_REG_CC_CURCD_U,
	BD71815_REG_CC_CURCD_L,
	BD71815_REG_VM_OCUR_THR_1,
	BD71815_REG_VM_OCUR_DUR_1,
	BD71815_REG_VM_OCUR_THR_2,
	BD71815_REG_VM_OCUR_DUR_2,
	BD71815_REG_VM_OCUR_THR_3,
	BD71815_REG_VM_OCUR_DUR_3,
	BD71815_REG_VM_OCUR_MON,
	BD71815_REG_VM_BTMP_OV_THR,
	BD71815_REG_VM_BTMP_OV_DUR,
	BD71815_REG_VM_BTMP_LO_THR,
	BD71815_REG_VM_BTMP_LO_DUR,
	BD71815_REG_VM_BTMP_MON,
	BD71815_REG_INT_EN_01,

	BD71815_REG_INT_EN_11		= 0x95,
	BD71815_REG_INT_EN_12,
	BD71815_REG_INT_STAT,
	BD71815_REG_INT_STAT_01,
	BD71815_