0 ˆÄÅ „ í¼çÃÁÇ?÷/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2016 Rockchip Electronics Co. Ltd. * Author: Xing Zheng */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H /* core clocks */ #define PLL_APLLL 1 #define PLL_APLLB 2 #define PLL_DPLL 3 #define PLL_CPLL 4 #define PLL_GPLL 5 #define PLL_NPLL 6 #define PLL_VPLL 7 #define ARMCLKL 8 #define ARMCLKB 9 /* sclk gates (special clocks) */ #define SCLK_I2C1 65 #define SCLK_I2C2 66 #define SCLK_I2C3 67 #define SCLK_I2C5 68 #define SCLK_I2C6 69 #define SCLK_I2C7 70 #define SCLK_SPI0 71 #define SCLK_SPI1 72 #define SCLK_SPI2 73 #define SCLK_SPI4 74 #define SCLK_SPI5 75 #define SCLK_SDMMC 76 #define SCLK_SDIO 77 #define SCLK_EMMC 78 #define SCLK_TSADC 79 #define SCLK_SARADC 80 #define SCLK_UART0 81 #define SCLK_UART1 82 #define SCLK_UART2 83 #define SCLK_UART3 84 #define SCLK_SPDIF_8CH 85 #define SCLK_I2S0_8CH 86 #define SCLK_I2S1_8CH 87 #define SCLK_I2S2_8CH 88 #define SCLK_I2S_8CH_OUT 89 #define SCLK_TIMER00 90 #define SCLK_TIMER01 91 #define SCLK_TIMER02 92 #define SCLK_TIMER03 93 #define SCLK_TIMER04 94 #define SCLK_TIMER05 95 #define SCLK_TIMER06 96 #define SCLK_TIMER07 97 #define SCLK_TIMER08 98 #define SCLK_TIMER09 99 #define SCLK_TIMER10 100 #define SCLK_TIMER11 101 #define SCLK_MACREF 102 #define SCLK_MAC_RX 103 #define SCLK_MAC_TX 104 #define SCLK_MAC 105 #define SCLK_MACREF_OUT 106 #define SCLK_VOP0_PWM 107 #define SCLK_VOP1_PWM 108 #define SCLK_RGA_CORE 109 #define SCLK_ISP0 110 #define SCLK_ISP1 111 #define SCLK_HDMI_CEC 112 #define SCLK_HDMI_SFR 113 #define SCLK_DP_CORE 114 #define SCLK_PVTM_CORE_L 115 #define SCLK_PVTM_CORE_B 116 #define SCLK_PVTM_GPU 117 #define SCLK_PVTM_DDR 118 #define SCLK_MIPIDPHY_REF 119 #define SCLK_MIPIDPHY_CFG 120 #define SCLK_HSICPHY 121 #define SCLK_USBPHY480M 122 #define SCLK_USB2PHY0_REF 123 #define SCLK_USB2PHY1_REF 124 #define SCLK_UPHY0_TCPDPHY_REF 125 #define SCLK_UPHY0_TCPDCORE 126 #define SCLK_UPHY1_TCPDPHY_REF 127 #define SCLK_UPHY1_TCPDCORE 128 #define SCLK_USB3OTG0_REF 129 #define SCLK_USB3OTG1_REF 130 #define SCLK_USB3OTG0_SUSPEND 131 #define SCLK_USB3OTG1_SUSPEND 132 #define SCLK_CRYPTO0 133 #define SCLK_CRYPTO1 134 #define SCLK_CCI_TRACE 135 #define SCLK_CS 136 #define SCLK_CIF_OUT 137 #define SCLK_PCIEPHY_REF 138 #define SCLK_PCIE_CORE 139 #define SCLK_M0_PERILP 140 #define SCLK_M0_PERILP_DEC 141 #define SCLK_CM0S 142 #define SCLK_DBG_NOC 143 #define SCLK_DBG_PD_CORE_B 144 #define SCLK_DBG_PD_CORE_L 145 #define SCLK_DFIMON0_TIMER 146 #define SCLK_DFIMON1_TIMER 147 #define SCLK_INTMEM0 148 #define SCLK_INTMEM1 149 #define SCLK_INTMEM2 150 #define SCLK_INTMEM3 151 #define SCLK_INTMEM4 152 #define SCLK_INTMEM5 153 #define SCLK_SDMMC_DRV 154 #define SCLK_SDMMC_SAMPLE 155 #define SCLK_SDIO_DRV 156 #define SCLK_SDIO_SAMPLE 157 #define SCLK_VDU_CORE 158 #define SCLK_VDU_CA 159 #define SCLK_PCIE_PM 160 #define SCLK_SPDIF_REC_DPTX 161 #define SCLK_DPHY_PLL 162 #define SCLK_DPHY_TX0_CFG 163 #define SCLK_DPHY_TX1RX1_CFG 164 #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 #define SCLK_DDRC 168 #define SCLK_TESTCLKOUT1 169 #define SCLK_TESTCLKOUT2 170 #define DCLK_VOP0 180 #define DCLK_VOP1 181 #define DCLK_VOP0_DIV 182 #define DCLK_VOP1_DIV 183 #define DCLK_M0_PERILP 184 #define DCLK_VOP0_FRAC 185 #define DCLK_VOP1_FRAC 186 #define FCLK_CM0S 190 /* aclk gates */ #define ACLK_PERIHP 192 #define ACLK_PERIHP_NOC 193 #define ACLK_PERILP0 194 #define ACLK_PERILP0_NOC 195 #define ACLK_PERF_PCIE 196 #define ACLK_PCIE 197 #define ACLK_INTMEM 198 #define ACLK_TZMA 199 #define ACLK_DCF 200 #define ACLK_CCI 201 #define ACLK_CCI_NOC0 202 #define ACLK_CCI_NOC1 203 #define ACLK_CCI_GRF 204 #define ACLK_CENTER 205 #define ACLK_CENTER_MAIN_NOC 206 #defin