Unknown  -_I|+5/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2014 MediaTek Inc. * Author: Shunli Wang */ #ifndef _DT_BINDINGS_CLK_MT2701_H #define _DT_BINDINGS_CLK_MT2701_H /* TOPCKGEN */ #define CLK_TOP_SYSPLL 1 #define CLK_TOP_SYSPLL_D2 2 #define CLK_TOP_SYSPLL_D3 3 #define CLK_TOP_SYSPLL_D5 4 #define CLK_TOP_SYSPLL_D7 5 #define CLK_TOP_SYSPLL1_D2 6 #define CLK_TOP_SYSPLL1_D4 7 #define CLK_TOP_SYSPLL1_D8 8 #define CLK_TOP_SYSPLL1_D16 9 #define CLK_TOP_SYSPLL2_D2 10 #define CLK_TOP_SYSPLL2_D4 11 #define CLK_TOP_SYSPLL2_D8 12 #define CLK_TOP_SYSPLL3_D2 13 #define CLK_TOP_SYSPLL3_D4 14 #define CLK_TOP_SYSPLL4_D2 15 #define CLK_TOP_SYSPLL4_D4 16 #define CLK_TOP_UNIVPLL 17 #define CLK_TOP_UNIVPLL_D2 18 #define CLK_TOP_UNIVPLL_D3 19 #define CLK_TOP_UNIVPLL_D5 20 #define CLK_TOP_UNIVPLL_D7 21 #define CLK_TOP_UNIVPLL_D26 22 #define CLK_TOP_UNIVPLL_D52 23 #define CLK_TOP_UNIVPLL_D108 24 #define CLK_TOP_USB_PHY48M 25 #define CLK_TOP_UNIVPLL1_D2 26 #define CLK_TOP_UNIVPLL1_D4 27 #define CLK_TOP_UNIVPLL1_D8 28 #define CLK_TOP_UNIVPLL2_D2 29 #define CLK_TOP_UNIVPLL2_D4 30 #define CLK_TOP_UNIVPLL2_D8 31 #define CLK_TOP_UNIVPLL2_D16 32 #define CLK_TOP_UNIVPLL2_D32 33 #define CLK_TOP_UNIVPLL3_D2 34 #define CLK_TOP_UNIVPLL3_D4 35 #define CLK_TOP_UNIVPLL3_D8 36 #define CLK_TOP_MSDCPLL 37 #define CLK_TOP_MSDCPLL_D2 38 #define CLK_TOP_MSDCPLL_D4 39 #define CLK_TOP_MSDCPLL_D8 40 #define CLK_TOP_MMPLL 41 #define CLK_TOP_MMPLL_D2 42 #define CLK_TOP_DMPLL 43 #define CLK_TOP_DMPLL_D2 44 #define CLK_TOP_DMPLL_D4 45 #define CLK_TOP_DMPLL_X2 46 #define CLK_TOP_TVDPLL 47 #define CLK_TOP_TVDPLL_D2 48 #define CLK_TOP_TVDPLL_D4 49 #define CLK_TOP_TVD2PLL 50 #define CLK_TOP_TVD2PLL_D2 51 #define CLK_TOP_HADDS2PLL_98M 52 #define CLK_TOP_HADDS2PLL_294M 53 #define CLK_TOP_HADDS2_FB 54 #define CLK_TOP_MIPIPLL_D2 55 #define CLK_TOP_MIPIPLL_D4 56 #define CLK_TOP_HDMIPLL 57 #define CLK_TOP_HDMIPLL_D2 58 #define CLK_TOP_HDMIPLL_D3 59 #define CLK_TOP_HDMI_SCL_RX 60 #define CLK_TOP_HDMI_0_PIX340M 61 #define CLK_TOP_HDMI_0_DEEP340M 62 #define CLK_TOP_HDMI_0_PLL340M 63 #define CLK_TOP_AUD1PLL_98M 64 #define CLK_TOP_AUD2PLL_90M 65 #define CLK_TOP_AUDPLL 66 #define CLK_TOP_AUDPLL_D4 67 #define CLK_TOP_AUDPLL_D8 68 #define CLK_TOP_AUDPLL_D16 69 #define CLK_TOP_AUDPLL_D24 70 #define CLK_TOP_ETHPLL_500M 71 #define CLK_TOP_VDECPLL 72 #define CLK_TOP_VENCPLL 73 #define CLK_TOP_MIPIPLL 74 #define CLK_TOP_ARMPLL_1P3G 75 #define CLK_TOP_MM_SEL 76 #define CLK_TOP_DDRPHYCFG_SEL 77 #define CLK_TOP_MEM_SEL 78 #define CLK_TOP_AXI_SEL 79 #define CLK_TOP_CAMTG_SEL 80 #define CLK_TOP_MFG_SEL 81 #define CLK_TOP_VDEC_SEL 82 #define CLK_TOP_PWM_SEL 83 #define CLK_TOP_MSDC30_0_SEL 84 #define CLK_TOP_USB20_SEL 85 #define CLK_TOP_SPI0_SEL 86 #define CLK_TOP_UART_SEL 87 #define CLK_TOP_AUDINTBUS_SEL 88 #define CLK_TOP_AUDIO_SEL 89 #define CLK_TOP_MSDC30_2_SEL 90 #define CLK_TOP_MSDC30_1_SEL 91 #define CLK_TOP_DPI1_SEL 92 #define CLK_TOP_DPI0_SEL 93 #define CLK_TOP_SCP_SEL 94 #define CLK_TOP_PMICSPI_SEL 95 #define CLK_TOP_APLL_SEL 96 #define CLK_TOP_HDMI_SEL 97 #define CLK_TOP_TVE_SEL 98 #define CLK_TOP_EMMC_HCLK_SEL 99 #define CLK_TOP_NFI2X_SEL 100 #define CLK_TOP_RTC_SEL 101 #define CLK_TOP_OSD_SEL 102 #define CLK_TOP_NR_SEL 103 #define CLK_TOP_DI_SEL 104 #define CLK_TOP_FLASH_SEL 105 #define CLK_TOP_ASM_M_SEL 106 #define CLK_TOP_ASM_I_SEL 107 #define CLK_TOP_INTDIR_SEL 108 #define CLK_TOP_HDMIRX_BIST_SEL 109 #define CLK_TOP_ETHIF_SEL 110 #define CLK_TOP_MS_CARD_SEL 111 #define CLK_TOP_ASM_H_SEL 112 #define CLK_TOP_SPI1_SEL 113 #define CLK_TOP_CMSYS_SEL 114 #define CLK_TOP_MSDC30_3_SEL 115 #define CLK_TOP_HDMIRX26_24_SEL 116 #define CLK_TOP_AUD2DVD_SEL 117 #define CLK_TOP_8BDAC_SEL 118 #define CLK_TOP_SPI2_SEL 119 #define CLK_TOP_AUD_MUX1_SEL 120 #d