(null)   p?_I|+( /* SPDX-License-Identifier: GPL-2.0-or-later */ #ifndef __SOUND_AK4113_H #define __SOUND_AK4113_H /* * Routines for Asahi Kasei AK4113 * Copyright (c) by Jaroslav Kysela , * Copyright (c) by Pavel Hofman , */ /* AK4113 registers */ /* power down */ #define AK4113_REG_PWRDN 0x00 /* format control */ #define AK4113_REG_FORMAT 0x01 /* input/output control */ #define AK4113_REG_IO0 0x02 /* input/output control */ #define AK4113_REG_IO1 0x03 /* interrupt0 mask */ #define AK4113_REG_INT0_MASK 0x04 /* interrupt1 mask */ #define AK4113_REG_INT1_MASK 0x05 /* DAT mask & DTS select */ #define AK4113_REG_DATDTS 0x06 /* receiver status 0 */ #define AK4113_REG_RCS0 0x07 /* receiver status 1 */ #define AK4113_REG_RCS1 0x08 /* receiver status 2 */ #define AK4113_REG_RCS2 0x09 /* RX channel status byte 0 */ #define AK4113_REG_RXCSB0 0x0a /* RX channel status byte 1 */ #define AK4113_REG_RXCSB1 0x0b /* RX channel status byte 2 */ #define AK4113_REG_RXCSB2 0x0c /* RX channel status byte 3 */ #define AK4113_REG_RXCSB3 0x0d /* RX channel status byte 4 */ #define AK4113_REG_RXCSB4 0x0e /* burst preamble Pc byte 0 */ #define AK4113_REG_Pc0 0x0f /* burst preamble Pc byte 1 */ #define AK4113_REG_Pc1 0x10 /* burst preamble Pd byte 0 */ #define AK4113_REG_Pd0 0x11 /* burst preamble Pd byte 1 */ #define AK4113_REG_Pd1 0x12 /* Q-subcode address + control */ #define AK4113_REG_QSUB_ADDR 0x13 /* Q-subcode track */ #define AK4113_REG_QSUB_TRACK 0x14 /* Q-subcode index */ #define AK4113_REG_QSUB_INDEX 0x15 /* Q-subcode minute */ #define AK4113_REG_QSUB_MINUTE 0x16 /* Q-subcode second */ #define AK4113_REG_QSUB_SECOND 0x17 /* Q-subcode frame */ #define AK4113_REG_QSUB_FRAME 0x18 /* Q-subcode zero */ #define AK4113_REG_QSUB_ZERO 0x19 /* Q-subcode absolute minute */ #define AK4113_REG_QSUB_ABSMIN 0x1a /* Q-subcode absolute second */ #define AK4113_REG_QSUB_ABSSEC 0x1b /* Q-subcode absolute frame */ #define AK4113_REG_QSUB_ABSFRM 0x1c /* sizes */ #define AK4113_REG_RXCSB_SIZE ((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1) #define AK4113_REG_QSUB_SIZE ((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\ +1) #define AK4113_WRITABLE_REGS (AK4113_REG_DATDTS + 1) /* AK4113_REG_PWRDN bits */ /* Channel Status Select */ #define AK4113_CS12 (1<<7) /* Block Start & C/U Output Mode */ #define AK4113_BCU (1<<6) /* Master Clock Operation Select */ #define AK4113_CM1 (1<<5) /* Master Clock Operation Select */ #define AK4113_CM0 (1<<4) /* Master Clock Frequency Select */ #define AK4113_OCKS1 (1<<3) /* Master Clock Frequency Select */ #define AK4113_OCKS0 (1<<2) /* 0 = power down, 1 = normal operation */ #define AK4113_PWN (1<<1) /* 0 = reset & initialize (except thisregister), 1 = normal operation */ #define AK4113_RST (1<<0) /* AK4113_REQ_FORMAT bits */ /* V/TX Output select: 0 = Validity Flag Output, 1 = TX */ #define AK4113_VTX (1<<7) /* Audio Data Control */ #define AK4113_DIF2 (1<<6) /* Audio Data Control */ #define AK4113_DIF1 (1<<5) /* Audio Data Control */ #define AK4113_DIF0 (1<<4) /* Deemphasis Autodetect Enable (1 = enable) */ #define AK4113_DEAU (1<<3) /* 32kHz-48kHz Deemphasis Control */ #define AK4113_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */ #define AK4113_DEM0 (1<<1) #define AK4113_DEM_OFF (AK4113_DEM0) #define AK4113_DEM_44KHZ (0) #define AK4113_DEM_48KHZ (AK4113_DEM1) #define AK4113_DEM_32KHZ (AK4113_DEM0|AK4113_DEM1) /* STDO: 16-bit, right justified */ #define AK4113_DIF_16R (0) /* STDO: 18-bit, right justified */ #define AK4113_DIF_18R (AK4113_DIF0) /* STDO: 20-bit, right justified */ #define AK4113_DIF_20R (AK4113_DIF1) /* STDO: 24-bit, right justified */ #define AK4113_DIF_24R (AK4113_DIF1|AK4113_DIF0) /* STDO: 24-bit, left justified */ #define AK4113_DIF_24L (AK4113_DIF2) /* STDO: I2S */ #define AK4113_DIF_24I2S (AK4113_DIF2|AK4113_DIF0) /* STDO: 24-bit, left justified; LRCLK, BICK = Input */ #define AK4113_DIF_I24L (AK4113_DIF2|AK4113_DIF1) /* STDO: I2S; LRCLK, BICK = Input */ #define AK4113_DIF_I24I2S (AK4113_DIF2|AK4