0 "l4( (  fD- o# SPDX-License-Identifier: GPL-2.0 ifeq ($(CONFIG_ARCH_OMAP2PLUS), y) obj-y += clk.o autoidle.o clockdomain.o clk-common = dpll.o composite.o divider.o gate.o \ fixed-factor.o mux.o apll.o \ clkt_dpll.o clkt_iclk.o clkt_dflt.o \ clkctrl.o obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \ clk-33xx-compat.o obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \ clk-3xxx.o dpll3xxx.o obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \ dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \ dpll3xxx.o dpll44xx.o obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \ clk-dra7-atl.o dpll3xxx.o \ dpll44xx.o clk-7xx-compat.o obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o \ clk-43xx-compat.o endif # CONFIG_ARCH_OMAP2PLUS obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o *l4( (  fB- l_I|+/* SPDX-License-Identifier: GPL-2.0-only */ /* * Defines for Mobile Industry Processor Interface (MIPI(R)) * Display Working Group standards: DSI, DCS, DBI, DPI * * Copyright (C) 2010 Guennadi Liakhovetski * Copyright (C) 2006 Nokia Corporation * Author: Imre Deak */ #ifndef MIPI_DISPLAY_H #define MIPI_DISPLAY_H /* MIPI DSI Processor-to-Peripheral transaction types */ enum { MIPI_DSI_V_SYNC_START = 0x01, MIPI_DSI_V_SYNC_END = 0x11, MIPI_DSI_H_SYNC_START = 0x21, MIPI_DSI_H_SYNC_END = 0x31, MIPI_DSI_COMPRESSION_MODE = 0x07, MIPI_DSI_END_OF_TRANSMISSION = 0x08, MIPI_DSI_COLOR_MODE_OFF = 0x02, MIPI_DSI_COLOR_MODE_ON = 0x12, MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, MIPI_DSI_DCS_SHORT_WRITE = 0x05, MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, MIPI_DSI_DCS_READ = 0x06, MIPI_DSI_EXECUTE_QUEUE = 0x16, MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, MIPI_DSI_NULL_PACKET = 0x09, MIPI_DSI_BLANKING_PACKET = 0x19, MIPI_DSI_GENERIC_LONG_WRITE = 0x29, MIPI_DSI_DCS_LONG_WRITE = 0x39, MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a, MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b, MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, }; /* MIPI DSI Peripheral-to-Processor transaction types */ enum { MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, }; /* MIPI DCS commands */ enum { MIPI_DCS_NOP = 0x00, MIPI_DCS_SOFT_RESET = 0x01, MIPI_DCS_GET_COMPRESSION_MODE = 0x03, MIPI_DCS_GET_DISPLAY_ID = 0x04, MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05, MIPI_DCS_GET_RED_CHANNEL = 0x06, MIPI_DCS_GET_GREEN_CHANNEL = 0x07, MIPI_DCS_GET_BLUE_CHANNEL = 0x08, MIPI_DCS_GET_DISPLAY_STATUS = 0x09, MIPI_DCS_GET_POWER_MODE = 0x0A, MIPI_DCS_GET_ADDRESS_MODE = 0x0B, MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, MIPI_DCS_GET_DISPLAY_MODE = 0x0D, MIPI_DCS_GET_