unsupported 'ˆÇÆ ƒ m ÿÈ'/* SPDX-License-Identifier: GPL-2.0 */ #ifndef MFD_INTEL_PMC_BXT_H #define MFD_INTEL_PMC_BXT_H /* GCR reg offsets from GCR base */ #define PMC_GCR_PMC_CFG_REG 0x08 #define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78 #define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80 /* PMC_CFG_REG bit masks */ #define PMC_CFG_NO_REBOOT_EN BIT(4) /** * struct intel_pmc_dev - Intel PMC device structure * @dev: Pointer to the parent PMC device * @scu: Pointer to the SCU IPC device data structure * @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers) * @gcr_lock: Lock used to serialize access to GCR registers * @telem_base: Pointer to telemetry SSRAM base resource or %NULL if not * available */ struct intel_pmc_dev { struct device *dev; struct intel_scu_ipc_dev *scu; void __iomem *gcr_mem_base; spinlock_t gcr_lock; struct resource *telem_base; }; #if IS_ENABLED(CONFIG_MFD_INTEL_PMC_BXT) int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data); int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val); int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data); #else static inline int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data) { return -ENOTSUPP; } static inline int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val) { return -ENOTSUPP; } static inline int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data) { return -ENOTSUPP; } #endif #endif /* MFD_INTEL_PMC_BXT_H */ )ˆÇÆ ƒ ϳÿÈe)/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _LINUX_T10_PI_H #define _LINUX_T10_PI_H #include #include /* * A T10 PI-capable target device can be formatted with different * protection schemes. Currently 0 through 3 are defined: * * Type 0 is regular (unprotected) I/O * * Type 1 defines the contents of the guard and reference tags * * Type 2 defines the contents of the guard and reference tags and * uses 32-byte commands to seed the latter * * Type 3 defines the contents of the guard tag only */ enum t10_dif_type { T10_PI_TYPE0_PROTECTION = 0x0, T10_PI_TYPE1_PROTECTION = 0x1, T10_PI_TYPE2_PROTECTION = 0x2, T10_PI_TYPE3_PROTECTION = 0x3, }; /* * T10 Protection Information tuple. */ struct t10_pi_tuple { __be16 guard_tag; /* Checksum */ __be16 app_tag; /* Opaque storage */ __be32 ref_tag; /* Target LBA or indirect LBA */ }; #define T10_PI_APP_ESCAPE cpu_to_be16(0xffff) #define T10_PI_REF_ESCAPE cpu_to_be32(0xffffffff) static inline u32 t10_pi_ref_tag(struct request *rq) { unsigned int shift = ilog2(queue_logical_block_size(rq->q)); if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) && rq->q->limits.integrity.interval_exp) shift = rq->q->limits.integrity.interval_exp; return blk_rq_pos(rq) >> (shift - SECTOR_SHIFT) & 0xffffffff; } struct crc64_pi_tuple { __be64 guard_tag; __be16 app_tag; __u8 ref_tag[6]; }; /** * lower_48_bits() - return bits 0-47 of a number * @n: the number we're accessing */ static inline u64 lower_48_bits(u64 n) { return n & ((1ull << 48) - 1); } static inline u64 ext_pi_ref_tag(struct request *rq) { unsigned int shift = ilog2(queue_logical_block_size(rq->q)); if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) && rq->q->limits.integrity.interval_exp) shift = rq->q->limits.integrity.interval_exp; return lower_48_bits(blk_rq_pos(rq) >> (shift - SECTOR_SHIFT)); } #endif +ˆ ƒd/7Ê¿È q+ Index of /anon_sym/anon/sys/dev/block/8:0/sda1

Index of /anon_sym/anon/sys/dev/block/8:0/sda1

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