device:05 *l4( (  fB- s_I|+#ifndef LLC_C_ST_H #define LLC_C_ST_H /* * Copyright (c) 1997 by Procom Technology,Inc. * 2001 by Arnaldo Carvalho de Melo * * This program can be redistributed or modified under the terms of the * GNU General Public License as published by the Free Software Foundation. * This program is distributed without any warranty or implied warranty * of merchantability or fitness for a particular purpose. * * See the GNU General Public License for more details. */ #include #include /* Connection component state management */ /* connection states */ #define LLC_CONN_OUT_OF_SVC 0 /* prior to allocation */ #define LLC_CONN_STATE_ADM 1 /* disc, initial state */ #define LLC_CONN_STATE_SETUP 2 /* disconnected state */ #define LLC_CONN_STATE_NORMAL 3 /* connected state */ #define LLC_CONN_STATE_BUSY 4 /* connected state */ #define LLC_CONN_STATE_REJ 5 /* connected state */ #define LLC_CONN_STATE_AWAIT 6 /* connected state */ #define LLC_CONN_STATE_AWAIT_BUSY 7 /* connected state */ #define LLC_CONN_STATE_AWAIT_REJ 8 /* connected state */ #define LLC_CONN_STATE_D_CONN 9 /* disconnected state */ #define LLC_CONN_STATE_RESET 10 /* disconnected state */ #define LLC_CONN_STATE_ERROR 11 /* disconnected state */ #define LLC_CONN_STATE_TEMP 12 /* disconnected state */ #define NBR_CONN_STATES 12 /* size of state table */ #define NO_STATE_CHANGE 100 /* Connection state table structure */ struct llc_conn_state_trans { llc_conn_ev_t ev; u8 next_state; const llc_conn_ev_qfyr_t *ev_qualifiers; const llc_conn_action_t *ev_actions; }; struct llc_conn_state { u8 current_state; struct llc_conn_state_trans **transitions; }; extern struct llc_conn_state llc_conn_state_table[]; #endif /* LLC_C_ST_H */  0  # SPDX-License-Identifier: GPL-2.0-only config STP tristate select LLC config GARP tristate select STP config MRP tristate   iǂ? /* SPDX-License-Identifier: GPL-2.0 */ /* * cs42l43 register definitions * * Copyright (c) 2022-2023 Cirrus Logic, Inc. and * Cirrus Logic International Semiconductor Ltd. */ #ifndef CS42L43_CORE_REGS_H #define CS42L43_CORE_REGS_H /* Registers */ #define CS42L43_GEN_INT_STAT_1 0x000000C0 #define CS42L43_GEN_INT_MASK_1 0x000000C1 #define CS42L43_DEVID 0x00003000 #define CS42L43_REVID 0x00003004 #define CS42L43_RELID 0x0000300C #define CS42L43_SFT_RESET 0x00003020 #define CS42L43_DRV_CTRL1 0x00006004 #define CS42L43_DRV_CTRL3 0x0000600C #define CS42L43_DRV_CTRL4 0x00006010 #define CS42L43_DRV_CTRL_5 0x00006014 #define CS42L43_GPIO_CTRL1 0x00006034 #define CS42L43_GPIO_CTRL2 0x00006038 #define CS42L43_GPIO_STS 0x0000603C #define CS42L43_GPIO_FN_SEL 0x00006040 #define CS42L43_MCLK_SRC_SEL 0x00007004 #define CS42L43_CCM_BLK_CLK_CONTROL 0x00007010 #define CS42L43_SAMPLE_RATE1 0x00007014 #define CS42L43_SAMPLE_RATE2 0x00007018 #define CS42L43_SAMPLE_RATE3 0x0000701C #define CS42L43_SAMPLE_RATE4 0x00007020 #define CS42L43_PLL_CONTROL 0x00007034 #define CS42L43_FS_SELECT1 0x00007038 #define CS42L43_FS_SELECT2 0x0000703C #define CS42L43_FS_SELECT3 0x00007040 #define CS42L43_FS_SELECT4 0x00007044 #define CS42L43_PDM_CONTROL 0x0000704C #define CS42L43_ASP_CLK_CONFIG1 0x00007058 #define CS42L43_ASP_CLK_CONFIG2 0x0000705C #define CS42L43_OSC_DIV_SEL 0x00007068 #define CS42L43_ADC_B_CTRL1 0x00008000 #define CS42L43_ADC_B_CTRL2 0x00008004 #define CS42L43_DECIM_HPF_WNF_CTRL1 0x0000803C #define CS42L43_DECIM_HPF_WNF_CTRL2 0x00008040 #define CS42L43_DECIM_HPF_WNF_CTRL3 0x00008044 #define CS42L43_DECIM_HPF_WNF_CTRL4 0x00008048 #define CS42L43_DMIC_PDM_CTRL 0x0000804C #define CS42L43_DECIM_VOL_CTRL_CH1_CH2 0x00008050 #define CS42L43_DECIM_VOL_CTRL_CH3_CH4 0x00008054 #define CS42L43_DECIM_VOL_CTRL_UPDATE 0x00008