1 a4()P@Wj@SFile not found.  _'/* SPDX-License-Identifier: GPL-2.0-only */ /* * libnvdimm - Non-volatile-memory Devices Subsystem * * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. */ #ifndef __LIBNVDIMM_H__ #define __LIBNVDIMM_H__ #include #include #include #include #include #include struct badrange_entry { u64 start; u64 length; struct list_head list; }; struct badrange { struct list_head list; spinlock_t lock; }; enum { /* unarmed memory devices may not persist writes */ NDD_UNARMED = 1, /* locked memory devices should not be accessed */ NDD_LOCKED = 2, /* memory under security wipes should not be accessed */ NDD_SECURITY_OVERWRITE = 3, /* tracking whether or not there is a pending device reference */ NDD_WORK_PENDING = 4, /* dimm supports namespace labels */ NDD_LABELING = 6, /* * dimm contents have changed requiring invalidation of CPU caches prior * to activation of a region that includes this device */ NDD_INCOHERENT = 7, /* dimm provider wants synchronous registration by __nvdimm_create() */ NDD_REGISTER_SYNC = 8, /* need to set a limit somewhere, but yes, this is likely overkill */ ND_IOCTL_MAX_BUFLEN = SZ_4M, ND_CMD_MAX_ELEM = 5, ND_CMD_MAX_ENVELOPE = 256, ND_MAX_MAPPINGS = 32, /* region flag indicating to direct-map persistent memory by default */ ND_REGION_PAGEMAP = 0, /* * Platform ensures entire CPU store data path is flushed to pmem on * system power loss. */ ND_REGION_PERSIST_CACHE = 1, /* * Platform provides mechanisms to automatically flush outstanding * write data from memory controler to pmem on system power loss. * (ADR) */ ND_REGION_PERSIST_MEMCTRL = 2, /* Platform provides asynchronous flush mechanism */ ND_REGION_ASYNC = 3, /* Region was created by CXL subsystem */ ND_REGION_CXL = 4, /* mark newly adjusted resources as requiring a label update */ DPA_RESOURCE_ADJUSTED = 1 << 0, }; struct nvdimm; struct nvdimm_bus_descriptor; typedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm, unsigned int cmd, void *buf, unsigned int buf_len, int *cmd_rc); struct device_node; struct nvdimm_bus_descriptor { const struct attribute_group **attr_groups; unsigned long cmd_mask; unsigned long dimm_family_mask; unsigned long bus_family_mask; struct module *module; char *provider_name; struct device_node *of_node; ndctl_fn ndctl; int (*flush_probe)(struct nvdimm_bus_descriptor *nd_desc); int (*clear_to_send)(struct nvdimm_bus_descriptor *nd_desc, struct nvdimm *nvdimm, unsigned int cmd, void *data); const struct nvdimm_bus_fw_ops *fw_ops; }; struct nd_cmd_desc { int in_num; int out_num; u32 in_sizes[ND_CMD_MAX_ELEM]; int out_sizes[ND_CMD_MAX_ELEM]; }; struct nd_interleave_set { /* v1.1 definition of the interleave-set-cookie algorithm */ u64 cookie1; /* v1.2 definition of the interleave-set-cookie algorithm */ u64 cookie2; /* compatibility with initial buggy Linux implementation */ u64 altcookie; guid_t type_guid; }; struct nd_mapping_desc { struct nvdimm *nvdimm; u64 start; u64 size; int position; }; struct nd_region; struct nd_region_desc { struct resource *res; struct nd_mapping_desc *mapping; u16 num_mappings; const struct attribute_group **attr_groups; struct nd_interleave_set *nd_set; void *provider_data; int num_lanes; int numa_node; int target_node; unsigned long flags; int memregion; struct device_node *of_node; int (*flush)(struct nd_region *nd_region, struct bio *bio); }; struct device; void *devm_nvdimm_memremap(struct device *dev, resource_size_t offset, size_t size, unsigned long flags); static inline void __iomem *devm_nvdimm_ioremap(struct device *dev, resource_size_t offset, size_t size) { return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0); } struct nvdimm_bus; /* * Note that separate bits for locked + unlocked are defined so that * 'flags == 0' corresp