pci:v00001AF4d00001004sv00001AF4sd00000008bc01sc00i00  N5_I|Mdv &K Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/class/input/input4/event2/subsystem/input0/capabilities

Index of /configAHR/Jump/0-coastlinecompg/anon_sym/anon/sys/class/input/input4/event2/subsystem/input0/capabilities

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 abs 2026-10-11 13:03 4.0K 
 ev 2026-10-11 13:03 4.0K 
 ff 2026-10-11 13:03 4.0K 
 key 2026-10-11 13:13 4.0K 
 led 2026-10-11 13:03 4.0K 
 msc 2026-10-11 13:03 4.0K 
 rel 2026-10-11 13:03 4.0K 
 snd 2026-10-11 13:03 4.0K 
 sw 2026-10-11 13:03 4.0K 
l4( (  fB- 0 u_I|+F/* SPDX-License-Identifier: GPL-2.0-only */ /* * CAN driver for PEAK System micro-CAN based adapters * * Copyright (C) 2003-2011 PEAK System-Technik GmbH * Copyright (C) 2011-2013 Stephane Grosjean */ #ifndef PUCAN_H #define PUCAN_H /* uCAN commands opcodes list (low-order 10 bits) */ #define PUCAN_CMD_NOP 0x000 #define PUCAN_CMD_RESET_MODE 0x001 #define PUCAN_CMD_NORMAL_MODE 0x002 #define PUCAN_CMD_LISTEN_ONLY_MODE 0x003 #define PUCAN_CMD_TIMING_SLOW 0x004 #define PUCAN_CMD_TIMING_FAST 0x005 #define PUCAN_CMD_SET_STD_FILTER 0x006 #define PUCAN_CMD_RESERVED2 0x007 #define PUCAN_CMD_FILTER_STD 0x008 #define PUCAN_CMD_TX_ABORT 0x009 #define PUCAN_CMD_WR_ERR_CNT 0x00a #define PUCAN_CMD_SET_EN_OPTION 0x00b #define PUCAN_CMD_CLR_DIS_OPTION 0x00c #define PUCAN_CMD_RX_BARRIER 0x010 #define PUCAN_CMD_END_OF_COLLECTION 0x3ff /* uCAN received messages list */ #define PUCAN_MSG_CAN_RX 0x0001 #define PUCAN_MSG_ERROR 0x0002 #define PUCAN_MSG_STATUS 0x0003 #define PUCAN_MSG_BUSLOAD 0x0004 #define PUCAN_MSG_CACHE_CRITICAL 0x0102 /* uCAN transmitted messages */ #define PUCAN_MSG_CAN_TX 0x1000 /* uCAN command common header */ struct __packed pucan_command { __le16 opcode_channel; u16 args[3]; }; /* return the opcode from the opcode_channel field of a command */ static inline u16 pucan_cmd_get_opcode(struct pucan_command *c) { return le16_to_cpu(c->opcode_channel) & 0x3ff; } #define