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  *   	€l–Ь4э( ©і( 	ЕЂfаB¦-яїѓ@_†I|ҐЏ+ВД 	a    	/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2007-2009 ST-Ericsson AB
 *
 * ABX500 core access functions.
 * The abx500 interface is used for the Analog Baseband chips.
 *
 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
 * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
 */

#include <linux/regulator/machine.h>

struct device;

#ifndef MFD_ABX500_H
#define MFD_ABX500_H

/**
 * struct abx500_init_setting
 * Initial value of the registers for driver to use during setup.
 */
struct abx500_init_settings {
	u8 bank;
	u8 reg;
	u8 setting;
};

int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
	u8 value);
int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
	u8 *value);
int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
	u8 first_reg, u8 *regvals, u8 numregs);
int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
	u8 first_reg, u8 *regvals, u8 numregs);
/**
 * abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
 *	target register
 *
 * @dev: The AB sub device.
 * @bank: The i2c bank number.
 * @bitmask: The bit mask to use.
 * @bitvalues: The new bit values.
 *
 * Updates the value of an AB register:
 * value -> ((value & ~bitmask) | (bitvalues & bitmask))
 */
int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
	u8 reg, u8 bitmask, u8 bitvalues);
int abx500_get_chip_id(struct device *dev);
int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);

struct abx500_ops {
	int (*get_chip_id) (struct device *);
	int (*get_register) (struct device *, u8, u8, u8 *);
	int (*set_register) (struct device *, u8, u8, u8);
	int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
	int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
	int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
	int (*event_registers_startup_state_get) (struct device *, u8 *);
	int (*startup_irq_enabled) (struct device *, unsigned int);
	void (*dump_all_banks) (struct device *);
};

int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
void abx500_remove_ops(struct device *dev);
#endif
     €їАѓ.9ѕВД 	>    /* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
 */

#ifndef _LINUX_NVME_RDMA_H
#define _LINUX_NVME_RDMA_H

#define NVME_RDMA_IP_PORT		4420

#define NVME_RDMA_MAX_QUEUE_SIZE 256
#define NVME_RDMA_MAX_METADATA_QUEUE_SIZE 128
#define NVME_RDMA_DEFAULT_QUEUE_SIZE 128

enum nvme_rdma_cm_fmt {
	NVME_RDMA_CM_FMT_1_0 = 0x0,
};

enum nvme_rdma_cm_status {
	NVME_RDMA_CM_INVALID_LEN	= 0x01,
	NVME_RDMA_CM_INVALID_RECFMT	= 0x02,
	NVME_RDMA_CM_INVALID_QID	= 0x03,
	NVME_RDMA_CM_INVALID_HSQSIZE	= 0x04,
	NVME_RDMA_CM_INVALID_HRQSIZE	= 0x05,
	NVME_RDMA_CM_NO_RSC		= 0x06,
	NVME_RDMA_CM_INVALID_IRD	= 0x07,
	NVME_RDMA_CM_INVALID_ORD	= 0x08,
	NVME_RDMA_CM_INVALID_CNTLID	= 0x09,
};

static inline const char *nvme_rdma_cm_msg(enum nvme_rdma_cm_status status)
{
	switch (status) {
	case NVME_RDMA_CM_INVALID_LEN:
		return "invalid length";
	case NVME_RDMA_CM_INVALID_RECFMT:
		return "invalid record format";
	case NVME_RDMA_CM_INVALID_QID:
		return "invalid queue ID";
	case NVME_RDMA_CM_INVALID_HSQSIZE:
		return "invalid host SQ size";
	case NVME_RDMA_CM_INVALID_HRQSIZE:
		return "invalid host RQ size";
	case NVME_RDMA_CM_NO_RSC:
		return "resource not found";
	case NVME_RDMA_CM_INVALID_IRD:
		return "invalid IRD";
	case NVME_RDMA_CM_INVALID_ORD:
		return "Invalid ORD";
	case NVME_RDMA_CM_INVALID_CNTLID:
		return "invalid controller ID";
	default:
		return "unrecognized reason";
	}
}

/**
 * struct nvme_rdma_cm_req - rdma connect request
 *
 * @recfmt:        format of the RDMA Private Data
 * @qid:           queue Identifier for the Admin or I