state = active io 0x70-0x77 irq 8 U YƿjU/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _TOOLS_ASM_BUG_H #define _TOOLS_ASM_BUG_H #include #include #define __WARN_printf(arg...) do { fprintf(stderr, arg); } while (0) #define WARN(condition, format...) ({ \ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) \ __WARN_printf(format); \ unlikely(__ret_warn_on); \ }) #define WARN_ON(condition) ({ \ int __ret_warn_on = !!(condition); \ if (unlikely(__ret_warn_on)) \ __WARN_printf("assertion failed at %s:%d\n", \ __FILE__, __LINE__); \ unlikely(__ret_warn_on); \ }) #define WARN_ON_ONCE(condition) ({ \ static int __warned; \ int __ret_warn_once = !!(condition); \ \ if (unlikely(__ret_warn_once && !__warned)) { \ __warned = true; \ WARN_ON(1); \ } \ unlikely(__ret_warn_once); \ }) #define WARN_ONCE(condition, format...) ({ \ static int __warned; \ int __ret_warn_once = !!(condition); \ \ if (unlikely(__ret_warn_once)) \ if (WARN(!__warned, format)) \ __warned = 1; \ unlikely(__ret_warn_once); \ }) #endif /* _TOOLS_ASM_BUG_H */ "Wli~ h8Eqn1h 703W{ "sr_version": { "major": 1, "minor": 1, "patch": 1 }, "sr_domain": { "soc": "msm", "domain": "adsp", "subdomain": "audio_pd", "qmi_instance_id": 74 }, "sr_service": [ { "provider": "tms", "service": "servreg", "service_data_valid": 0, "service_data": 0, "dcomment": "data can be used to configure ACK timeout.Make data_valid 1 as well.Unit is second" }, { "provider": "avs", "service": "audio", "service_data_valid": 0, "service_data": 0, "dcomment": "No comment" } ] }YYFile not found. [[File not found. ] 737] Index of /FSS-OZR/root/usr/lib/firmware/intel-ucode

Index of /FSS-OZR/root/usr/lib/firmware/intel-ucode

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_ dM?_/* SPDX-License-Identifier: GPL-2.0 */ #ifndef LINUX_BCMA_DRIVER_CC_H_ #define LINUX_BCMA_DRIVER_CC_H_ #include #include #include /** ChipCommon core registers. **/ #define BCMA_CC_ID 0x0000 #define BCMA_CC_ID_ID 0x0000FFFF #define BCMA_CC_ID_ID_SHIFT 0 #define BCMA_CC_ID_REV 0x000F0000 #define BCMA_CC_ID_REV_SHIFT 16 #define BCMA_CC_ID_PKG 0x00F00000 #define BCMA_CC_ID_PKG_SHIFT 20 #define BCMA_CC_ID_NRCORES 0x0F000000 #define BCMA_CC_ID_NRCORES_SHIFT 24 #define BCMA_CC_ID_TYPE 0xF0000000 #define BCMA_CC_ID_TYPE_SHIFT 28 #define BCMA_CC_CAP 0x0004 /* Capabilities */ #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */ #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ #define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */ #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ #define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */ #define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */ #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial