0000000000000000000000000000110010000000000000000000000000000000 #1ˆl–Ü4ý(© ³( Å €fàD¦-ÿÊ ƒqñ7ÆÃÍ 1/* SPDX-License-Identifier: GPL-2.0 */ /* * AMD SEV header common between the guest and the hypervisor. * * Author: Brijesh Singh */ #ifndef __ASM_X86_SEV_COMMON_H #define __ASM_X86_SEV_COMMON_H #define GHCB_MSR_INFO_POS 0 #define GHCB_DATA_LOW 12 #define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1) #define GHCB_DATA(v) \ (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW) /* SEV Information Request/Response */ #define GHCB_MSR_SEV_INFO_RESP 0x001 #define GHCB_MSR_SEV_INFO_REQ 0x002 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \ /* GHCBData[63:48] */ \ ((((_max) & 0xffff) << 48) | \ /* GHCBData[47:32] */ \ (((_min) & 0xffff) << 32) | \ /* GHCBData[31:24] */ \ (((_cbit) & 0xff) << 24) | \ GHCB_MSR_SEV_INFO_RESP) #define GHCB_MSR_INFO(v) ((v) & 0xfffUL) #define GHCB_MSR_PROTO_MAX(v) (((v) >> 48) & 0xffff) #define GHCB_MSR_PROTO_MIN(v) (((v) >> 32) & 0xffff) /* CPUID Request/Response */ #define GHCB_MSR_CPUID_REQ 0x004 #define GHCB_MSR_CPUID_RESP 0x005 #define GHCB_MSR_CPUID_FUNC_POS 32 #define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff #define GHCB_MSR_CPUID_VALUE_POS 32 #define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff #define GHCB_MSR_CPUID_REG_POS 30 #define GHCB_MSR_CPUID_REG_MASK 0x3 #define GHCB_CPUID_REQ_EAX 0 #define GHCB_CPUID_REQ_EBX 1 #define GHCB_CPUID_REQ_ECX 2 #define GHCB_CPUID_REQ_EDX 3 #define GHCB_CPUID_REQ(fn, reg) \ /* GHCBData[11:0] */ \ (GHCB_MSR_CPUID_REQ | \ /* GHCBData[31:12] */ \ (((unsigned long)(reg) & 0x3) << 30) | \ /* GHCBData[63:32] */ \ (((unsigned long)fn) << 32)) /* AP Reset Hold */ #define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 #define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 #define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) /* Preferred GHCB GPA Request */ #define GHCB_MSR_PREF_GPA_REQ 0x010 #define GHCB_MSR_GPA_VALUE_POS 12 #define GHCB_MSR_GPA_VALUE_MASK GENMASK_ULL(51, 0) #define GHCB_MSR_PREF_GPA_RESP 0x011 #define GHCB_MSR_PREF_GPA_NONE 0xfffffffffffff /* GHCB GPA Register */ #define GHCB_MSR_REG_GPA_REQ 0x012 #define GHCB_MSR_REG_GPA_REQ_VAL(v) \ /* GHCBData[63:12] */ \ (((u64)((v) & GENMASK_ULL(51, 0)) << 12) | \ /* GHCBData[11:0] */ \ GHCB_MSR_REG_GPA_REQ) #define GHCB_MSR_REG_GPA_RESP 0x013 #define GHCB_MSR_REG_GPA_RESP_VAL(v) \ /* GHCBData[63:12] */ \ (((u64)(v) & GENMASK_ULL(63, 12)) >> 12) /* * SNP Page State Change Operation * * GHCBData[55:52] - Page operation: * 0x0001 Page assignment, Private * 0x0002 Page assignment, Shared */ enum psc_op { SNP_PAGE_STATE_PRIVATE = 1, SNP_PAGE_STATE_SHARED, }; #define GHCB_MSR_PSC_REQ 0x014 #define GHCB_MSR_PSC_REQ_GFN(gfn, op) \ /* GHCBData[55:52] */ \ (((u64)((op) & 0xf) << 52) | \ /* GHCBData[51:12] */ \ ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \ /* GHCBData[11:0] */ \ GHCB_MSR_PSC_REQ) #define GHCB_MSR_PSC_REQ_TO_GFN(msr) (((msr) & GENMASK_ULL(51, 12)) >> 12) #define GHCB_MSR_PSC_REQ_TO_OP(msr) (((msr) & GENMASK_ULL(55, 52)) >> 52) #define GHCB_MSR_PSC_RESP 0x015 #define GHCB_MSR_PSC_RESP_VAL(val) \ /* GHCBData[63:32] */ \ (((u64)(val) & GENMASK_ULL(63, 32)) >> 32) /* Set highest bit as a generic error response */ #define GHCB_MSR_PSC_RESP_ERROR (BIT_ULL(63) | GHCB_MSR_PSC_RESP) /* GHCB Run at VMPL Request/Response */ #define GHCB_MSR_VMPL_REQ 0x016 #define GHCB_MSR_VMPL_REQ_LEVEL(v) \ /* GHCBData[39:32] */ \ (((u64)(v) & GENMASK_ULL(7, 0) << 32) | \ /* GHCBDdata[11:0] */ \ GHCB_MSR_VMPL_REQ) #define GHCB_MSR_VMPL_RESP 0x017 #define GHCB_MSR_VMPL_RESP_VAL(v) \ /* GHCBData[63:32] */ \ (((u64)(v) & GENMASK_ULL(63, 32)) >> 32) /* GHCB Hypervisor Feature Request/Response */ #define GHCB_MSR_HV_FT_REQ 0x080 #define GHCB_MSR_HV_FT_RESP 0x081 #define GHCB_MSR_HV_FT_POS 12 #define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) #define GHCB_MSR_HV_FT_RESP_VAL(v) \ /* GHCBData[63:1