(null) !; 791azD  ?qţ; Index of /anon_sym/anon/proc/thread-self/root/var/cache/kcare/dumps

Index of /anon_sym/anon/proc/thread-self/root/var/cache/kcare/dumps

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= hľ?=/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Driver for Realtek PCI-Express card reader * * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. * * Author: * Wei WANG */ #ifndef __RTSX_PCI_H #define __RTSX_PCI_H #include #include #include #define MAX_RW_REG_CNT 1024 #define RTSX_HCBAR 0x00 #define RTSX_HCBCTLR 0x04 #define STOP_CMD (0x01 << 28) #define READ_REG_CMD 0 #define WRITE_REG_CMD 1 #define CHECK_REG_CMD 2 #define RTSX_HDBAR 0x08 #define RTSX_SG_INT 0x04 #define RTSX_SG_END 0x02 #define RTSX_SG_VALID 0x01 #define RTSX_SG_NO_OP 0x00 #define RTSX_SG_TRANS_DATA (0x02 << 4) #define RTSX_SG_LINK_DESC (0x03 << 4) #define RTSX_HDBCTLR 0x0C #define SDMA_MODE 0x00 #define ADMA_MODE (0x02 << 26) #define STOP_DMA (0x01 << 28) #define TRIG_DMA (0x01 << 31) #define RTSX_HAIMR 0x10 #define HAIMR_TRANS_START (0x01 << 31) #define HAIMR_READ 0x00 #define HAIMR_WRITE (0x01 << 30) #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ) #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE) #define HAIMR_TRANS_END (HAIMR_TRANS_START) #define RTSX_BIPR 0x14 #define CMD_DONE_INT (1 << 31) #define DATA_DONE_INT (1 << 30) #define TRANS_OK_INT (1 << 29) #define TRANS_FAIL_INT (1 << 28) #define XD_INT (1 << 27) #define MS_INT (1 << 26) #define SD_INT (1 << 25) #define GPIO0_INT (1 << 24) #define OC_INT (1 << 23) #define SD_WRITE_PROTECT (1 << 19) #define XD_EXIST (1 << 18) #define MS_EXIST (1 << 17) #define SD_EXIST (1 << 16) #define DELINK_INT GPIO0_INT #define MS_OC_INT (1 << 23) #define SD_OVP_INT (1 << 23) #define SD_OC_INT (1 << 22) #define CARD_INT (XD_INT | MS_INT | SD_INT) #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \ CARD_INT | GPIO0_INT | OC_INT) #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) #define RTSX_BIER 0x18 #define CMD_DONE_INT_EN (1 << 31) #define DATA_DONE_INT_EN (1 << 30) #define TRANS_OK_INT_EN (1 << 29) #define TRANS_FAIL_INT_EN (1 << 28) #define XD_INT_EN (1 << 27) #define MS_INT_EN (1 << 26) #define SD_INT_EN (1 << 25) #define GPIO0_INT_EN (1 << 24) #define OC_INT_EN (1 << 23) #define DELINK_INT_EN GPIO0_INT_EN #define MS_OC_INT_EN (1 << 23) #define SD_OVP_INT_EN (1 << 23) #define SD_OC_INT_EN (1 << 22) #define RTSX_DUM_REG 0x1C /* * macros for easy use */ #define rtsx_pci_writel(pcr, reg, value) \ iowrite32(value, (pcr)->remap_addr + reg) #define rtsx_pci_readl(pcr, reg) \ ioread32((pcr)->remap_addr + reg) #define rtsx_pci_writew(pcr, reg, value) \ iowrite16(value, (pcr)->remap_addr + reg) #define rtsx_pci_readw(pcr, reg) \ ioread16((pcr)->remap_addr + reg) #define rtsx_pci_writeb(pcr, reg, value) \ iowrite8(value, (pcr)->remap_addr + reg) #define rtsx_pci_readb(pcr, reg) \ ioread8((pcr)->remap_addr + reg) #define STATE_TRANS_NONE 0 #define STATE_TRANS_CMD 1 #define STATE_TRANS_BUF 2 #define STATE_TRANS_SG 3 #