0 +l4( (  fB- ^i_I|+.I/* SPDX-License-Identifier: GPL-2.0 */ /* * Functions to access TPS65219 Power Management IC. * * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ */ #ifndef MFD_TPS65219_H #define MFD_TPS65219_H #include #include #include struct regmap; struct regmap_irq_chip_data; #define TPS65219_1V35 1350000 #define TPS65219_1V8 1800000 /* TPS chip id list */ #define TPS65219 0xF0 /* I2C ID for TPS65219 part */ #define TPS65219_I2C_ID 0x24 /* All register addresses */ #define TPS65219_REG_TI_DEV_ID 0x00 #define TPS65219_REG_NVM_ID 0x01 #define TPS65219_REG_ENABLE_CTRL 0x02 #define TPS65219_REG_BUCKS_CONFIG 0x03 #define TPS65219_REG_LDO4_VOUT 0x04 #define TPS65219_REG_LDO3_VOUT 0x05 #define TPS65219_REG_LDO2_VOUT 0x06 #define TPS65219_REG_LDO1_VOUT 0x07 #define TPS65219_REG_BUCK3_VOUT 0x8 #define TPS65219_REG_BUCK2_VOUT 0x9 #define TPS65219_REG_BUCK1_VOUT 0xA #define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB #define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC #define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD #define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE #define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF #define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10 #define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11 #define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12 #define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13 #define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14 #define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15 #define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16 #define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17 #define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18 #define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D #define TPS65219_REG_GENERAL_CONFIG 0x1E #define TPS65219_REG_MFP_1_CONFIG 0x1F #define TPS65219_REG_MFP_2_CONFIG 0x20 #define TPS65219_REG_STBY_1_CONFIG 0x21 #define TPS65219_REG_STBY_2_CONFIG 0x22 #define TPS65219_REG_OC_DEGL_CONFIG 0x23 /* 'sub irq' MASK registers */ #define TPS65219_REG_INT_MASK_UV 0x24 #define TPS65219_REG_MASK_CONFIG 0x25 #define TPS65219_REG_I2C_ADDRESS_REG 0x26 #define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27 #define TPS65219_REG_MANUFACTURING_VER 0x28 #define TPS65219_REG_MFP_CTRL 0x29 #define TPS65219_REG_DISCHARGE_CONFIG 0x2A /* main irq registers */ #define TPS65219_REG_INT_SOURCE 0x2B /* 'sub irq' registers */ #define TPS65219_REG_INT_LDO_3_4 0x2C #define TPS65219_REG_INT_LDO_1_2 0x2D #define TPS65219_REG_INT_BUCK_3 0x2E #define TPS65219_REG_INT_BUCK_1_2 0x2F #define TPS65219_REG_INT_SYSTEM 0x30 #define TPS65219_REG_INT_RV 0x31 #define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32 #define TPS65219_REG_INT_PB 0x33 #define TPS65219_REG_INT_LDO_3_4_POS 0 #define TPS65219_REG_INT_LDO_1_2_POS 1 #define TPS65219_REG_INT_BUCK_3_POS 2 #define TPS65219_REG_INT_BUCK_1_2_POS 3 #define TPS65219_REG_INT_SYS_POS 4 #define TPS65219_REG_INT_RV_POS 5 #define TPS65219_REG_INT_TO_RV_POS 6 #define TPS65219_REG_INT_PB_POS 7 #define TPS65219_REG_USER_NVM_CMD 0x34 #define TPS65219_REG_POWER_UP_STATUS 0x35 #define TPS65219_REG_SPARE_2 0x36 #define TPS65219_REG_SPARE_3 0x37 #define TPS65219_REG_FACTORY_CONFIG_2 0x41 /* Register field definitions */ #define TPS65219_DEVID_REV_MASK GENMASK(7, 0) #define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0) #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6) #define TPS65219_BUCKS_BW_SEL_MASK BIT(7) #define LDO_BYP_SHIFT 6 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT) #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7) /* Regulators enable control */ #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0) #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1) #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2) #define TPS65219_ENABLE_LDO1_EN_MASK