1 #ˆÂË „ ¬¾÷Á¾Í?÷#// SPDX-License-Identifier: GPL-2.0 /* * R8A66597 driver platform data * * Copyright (C) 2009 Renesas Solutions Corp. * * Author : Yoshihiro Shimoda */ #ifndef __LINUX_USB_R8A66597_H #define __LINUX_USB_R8A66597_H #define R8A66597_PLATDATA_XTAL_12MHZ 0x01 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03 struct r8a66597_platdata { /* This callback can control port power instead of DVSTCTR register. */ void (*port_power)(int port, int power); /* This parameter is for BUSWAIT */ u16 buswait; /* set one = on chip controller, set zero = external controller */ unsigned on_chip:1; /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */ unsigned xtal:2; /* set one = 3.3V, set zero = 1.5V */ unsigned vif:1; /* set one = big endian, set zero = little endian */ unsigned endian:1; /* (external controller only) set one = WR0_N shorted to WR1_N */ unsigned wr0_shorted_to_wr1:1; /* set one = using SUDMAC */ unsigned sudmac:1; }; /* Register definitions */ #define SYSCFG0 0x00 #define SYSCFG1 0x02 #define SYSSTS0 0x04 #define SYSSTS1 0x06 #define DVSTCTR0 0x08 #define DVSTCTR1 0x0A #define TESTMODE 0x0C #define PINCFG 0x0E #define DMA0CFG 0x10 #define DMA1CFG 0x12 #define CFIFO 0x14 #define D0FIFO 0x18 #define D1FIFO 0x1C #define CFIFOSEL 0x20 #define CFIFOCTR 0x22 #define CFIFOSIE 0x24 #define D0FIFOSEL 0x28 #define D0FIFOCTR 0x2A #define D1FIFOSEL 0x2C #define D1FIFOCTR 0x2E #define INTENB0 0x30 #define INTENB1 0x32 #define INTENB2 0x34 #define BRDYENB 0x36 #define NRDYENB 0x38 #define BEMPENB 0x3A #define SOFCFG 0x3C #define INTSTS0 0x40 #define INTSTS1 0x42 #define INTSTS2 0x44 #define BRDYSTS 0x46 #define NRDYSTS 0x48 #define BEMPSTS 0x4A #define FRMNUM 0x4C #define UFRMNUM 0x4E #define USBADDR 0x50 #define USBREQ 0x54 #define USBVAL 0x56 #define USBINDX 0x58 #define USBLENG 0x5A #define DCPCFG 0x5C #define DCPMAXP 0x5E #define DCPCTR 0x60 #define PIPESEL 0x64 #define PIPECFG 0x68 #define PIPEBUF 0x6A #define PIPEMAXP 0x6C #define PIPEPERI 0x6E #define PIPE1CTR 0x70 #define PIPE2CTR 0x72 #define PIPE3CTR 0x74 #define PIPE4CTR 0x76 #define PIPE5CTR 0x78 #define PIPE6CTR 0x7A #define PIPE7CTR 0x7C #define PIPE8CTR 0x7E #define PIPE9CTR 0x80 #define PIPE1TRE 0x90 #define PIPE1TRN 0x92 #define PIPE2TRE 0x94 #define PIPE2TRN 0x96 #define PIPE3TRE 0x98 #define PIPE3TRN 0x9A #define PIPE4TRE 0x9C #define PIPE4TRN 0x9E #define PIPE5TRE 0xA0 #define PIPE5TRN 0xA2 #define DEVADD0 0xD0 #define DEVADD1 0xD2 #define DEVADD2 0xD4 #define DEVADD3 0xD6 #define DEVADD4 0xD8 #define DEVADD5 0xDA #define DEVADD6 0xDC #define DEVADD7 0xDE #define DEVADD8 0xE0 #define DEVADD9 0xE2 #define DEVADDA 0xE4 /* System Configuration Control Register */ #define XTAL 0xC000 /* b15-14: Crystal selection */ #define XTAL48 0x8000 /* 48MHz */ #define XTAL24 0x4000 /* 24MHz */ #define XTAL12 0x0000 /* 12MHz */ #define XCKE 0x2000 /* b13: External clock enable */ #define PLLC 0x0800 /* b11: PLL control */ #define SCKE 0x0400 /* b10: USB clock enable */ #define PCSDIS 0x0200 /* b9: not CS wakeup */ #define LPSME 0x0100 /* b8: Low power sleep mode */ #define HSE 0x0080 /* b7: Hi-speed enable */ #define DCFM 0x0040 /* b6: Controller function select */ #define DRPD 0x0020 /* b5: D+/- pull down control */ #define DPRPU 0x0010 /* b4: D+ pull up control */ #define USBE 0x0001 /* b0: USB module operation enable */ /* System Configuration Status Register */ #define OVCBIT 0x8000 /* b15-14: Over-current bit */ #define OVCMON 0xC000 /* b15-14: Over-current monitor */ #define SOFEA 0x0020 /* b5: SOF monitor */ #define IDMON 0x0004 /* b3: ID-pin monitor */ #define LNST 0x0003 /* b1-0: D+, D- line status */ #define SE1 0x0003 /* SE1 */ #define FS_KSTS 0x0002 /* Full-Speed K State */ #define FS_JSTS 0x0001 /* Full-Speed J State */ #define LS_JSTS 0x0002 /* Low-Speed J State */ #define LS_KSTS 0x0001 /* Low-Speed K State */ #define