D0 +l4( (  fB- n8_I|+=4/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Universal Flash Storage Host controller driver * Copyright (C) 2011-2013 Samsung India Software Operations * * Authors: * Santosh Yaraganavi * Vinayak Holikatti */ #ifndef _UFSHCI_H #define _UFSHCI_H #include #include enum { TASK_REQ_UPIU_SIZE_DWORDS = 8, TASK_RSP_UPIU_SIZE_DWORDS = 8, ALIGNED_UPIU_SIZE = 512, }; /* UFSHCI Registers */ enum { REG_CONTROLLER_CAPABILITIES = 0x00, REG_MCQCAP = 0x04, REG_UFS_VERSION = 0x08, REG_EXT_CONTROLLER_CAPABILITIES = 0x0C, REG_CONTROLLER_PID = 0x10, REG_CONTROLLER_MID = 0x14, REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18, REG_INTERRUPT_STATUS = 0x20, REG_INTERRUPT_ENABLE = 0x24, REG_CONTROLLER_STATUS = 0x30, REG_CONTROLLER_ENABLE = 0x34, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38, REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C, REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40, REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44, REG_UIC_ERROR_CODE_DME = 0x48, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C, REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50, REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54, REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58, REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C, REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60, REG_UTP_TASK_REQ_LIST_BASE_L = 0x70, REG_UTP_TASK_REQ_LIST_BASE_H = 0x74, REG_UTP_TASK_REQ_DOOR_BELL = 0x78, REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C, REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80, REG_UIC_COMMAND = 0x90, REG_UIC_COMMAND_ARG_1 = 0x94, REG_UIC_COMMAND_ARG_2 = 0x98, REG_UIC_COMMAND_ARG_3 = 0x9C, UFSHCI_REG_SPACE_SIZE = 0xA0, REG_UFS_CCAP = 0x100, REG_UFS_CRYPTOCAP = 0x104, REG_UFS_MEM_CFG = 0x300, REG_UFS_MCQ_CFG = 0x380, REG_UFS_ESILBA = 0x384, REG_UFS_ESIUBA = 0x388, UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400, }; /* Controller capability masks */ enum { MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F, MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF, MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00, MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000, MASK_EHSLUTRD_SUPPORTED = 0x00400000, MASK_AUTO_HIBERN8_SUPPORT = 0x00800000, MASK_64_ADDRESSING_SUPPORT = 0x01000000, MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000, MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000, MASK_CRYPTO_SUPPORT = 0x10000000, MASK_LSDB_SUPPORT = 0x20000000, MASK_MCQ_SUPPORT = 0x40000000, }; /* MCQ capability mask */ enum { MASK_EXT_IID_SUPPORT = 0x00000400, }; enum { REG_SQATTR = 0x0, REG_SQLBA = 0x4, REG_SQUBA = 0x8, REG_SQDAO = 0xC, REG_SQISAO = 0x10, REG_CQATTR = 0x20, REG_CQLBA = 0x24, REG_CQUBA = 0x28, REG_CQDAO = 0x2C, REG_CQISAO = 0x30, }; enum { REG_SQHP = 0x0, REG_SQTP = 0x4, REG_SQRTC = 0x8, REG_SQCTI = 0xC, REG_SQRTS = 0x10, }; enum { REG_CQHP = 0x0, REG_CQTP = 0x4, }; enum { REG_CQIS = 0x0, REG_CQIE = 0x4, }; enum { SQ_START = 0x0, SQ_STOP = 0x1, SQ_ICU = 0x2, }; enum { SQ_STS = 0x1, SQ_CUS = 0x2, }; #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4) #define UFS_MASK(mask, offset) ((mask) << (offset)) /* UFS Version 08h */ #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) #define UFSHCD_NUM_RESERVED 1 /* * Controller UFSHCI version * - 2.x and newer use the following scheme: * major << 8 + minor << 4 * - 1.x has been converted to match this in * ufshcd_get_ufs_version() */ static inline u32 ufshci_version(u32 major, u32 minor) { return (major << 8) + (minor << 4); } /* * HCDDID - Host Controller Identification Descriptor * - Device ID and Device Class 10h */ #define DEVICE_CLASS UFS_MASK(0xFFFF, 0) #define DEVICE_ID UFS_MASK(0xFF, 24) /* * HCPMID - Host Controller Identification Descriptor * - Product/Manufacturer ID 14h */ #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) /* AHIT - Auto-Hibernate Idle Timer */ #define UFSHCI_AHIBERN8_TIMER_MASK