15 + l4( (  fB- li_I|+? /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ /* QLogic qed NIC Driver * Copyright (c) 2015-2016 QLogic Corporation * Copyright (c) 2019-2021 Marvell International Ltd. */ #ifndef _COMMON_HSI_H #define _COMMON_HSI_H #include #include #include #include /* dma_addr_t manip */ #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff)) #define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16)) #define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x)) #define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x)) #define DMA_REGPAIR_LE(x, val) do { \ (x).hi = DMA_HI_LE((val)); \ (x).lo = DMA_LO_LE((val)); \ } while (0) #define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo)) #define HILO_64(hi, lo) \ HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64) #define HILO_64_REGPAIR(regpair) ({ \ typeof(regpair) __regpair = (regpair); \ HILO_64(__regpair.hi, __regpair.lo); }) #define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair)) #ifndef __COMMON_HSI__ #define __COMMON_HSI__ /********************************/ /* PROTOCOL COMMON FW CONSTANTS */ /********************************/ #define X_FINAL_CLEANUP_AGG_INT 1 #define EVENT_RING_PAGE_SIZE_BYTES 4096 #define NUM_OF_GLOBAL_QUEUES 128 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 #define ISCSI_CDU_TASK_SEG_TYPE 0 #define FCOE_CDU_TASK_SEG_TYPE 0 #define RDMA_CDU_TASK_SEG_TYPE 1 #define ETH_CDU_TASK_SEG_TYPE 2 #define FW_ASSERT_GENERAL_ATTN_IDX 32 /* Queue Zone sizes in bytes */ #define TSTORM_QZONE_SIZE 8 #define MSTORM_QZONE_SIZE 16 #define USTORM_QZONE_SIZE 8 #define XSTORM_QZONE_SIZE 8 #define YSTORM_QZONE_SIZE 0 #define PSTORM_QZONE_SIZE 0 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 #define ETH_MAX_RXQ_VF_DEFAULT 16 #define ETH_MAX_RXQ_VF_DOUBLE 48 #define ETH_MAX_RXQ_VF_QUAD 112 #define ETH_RGSRC_CTX_SIZE 6 #define ETH_TGSRC_CTX_SIZE 6 /********************************/ /* CORE (LIGHT L2) FW CONSTANTS */ /********************************/ #define CORE_LL2_MAX_RAMROD_PER_CON 8 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 /* Number of LL2 RAM based queues */ #define MAX_NUM_LL2_RX_RAM_QUEUES 32 /* Number of LL2 context based queues */ #define MAX_NUM_LL2_RX_CTX_QUEUES 208 #define MAX_NUM_LL2_RX_QUEUES \ (MAX_NUM_LL2_RX_RAM_QUEUES + MAX_NUM_LL2_RX_CTX_QUEUES) #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 #define FW_MAJOR_VERSION 8 #define FW_MINOR_VERSION 59 #define FW_REVISION_VERSION 1 #define FW_ENGINEERING_VERSION 0 /***********************/ /* COMMON HW CONSTANTS */ /***********************/ /* PCI functions */ #define MAX_NUM_PORTS_K2 (4) #define MAX_NUM_PORTS_BB (2) #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) #define MAX_NUM_PFS_K2 (16) #define MAX_NUM_PFS_BB (8) #define MAX_NUM_PFS (MAX_NUM_PFS_K2) #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ #define MAX_NUM_VFS_K2 (192) #define MAX_NUM_VFS_BB (120) #define MAX_NUM_VFS (MAX_NUM_VFS_K2) #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) #define MAX_NUM_FUNCTIONS (MAX_FUNCTION_NUMBER_K2) #define MAX_NUM_VPORTS_K2 (208) #define MAX_NUM_VPORTS_BB (160) #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) #define MAX_NUM_L2_QUEUES_K2 (320) #define MAX_NUM_L2_QUEUES_BB (256) #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ #define NUM_PHYS_TCS_4PORT_K2 (4) #define NUM_OF_PHYS_TCS (8) #define PURE_LB_TC NUM_OF_PHYS_TCS #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) /* CIDs */ #define NUM_