0x001c0000 ˆÀÉ ƒ^k¿ÁÇ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Header file for device driver Hi6421 PMIC * * Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd. * http://www.hisilicon.com * Copyright (c) <2013-2014> Linaro Ltd. * https://www.linaro.org * * Author: Guodong Xu */ #ifndef __HI6421_PMIC_H #define __HI6421_PMIC_H /* Hi6421 registers are mapped to memory bus in 4 bytes stride */ #define HI6421_REG_TO_BUS_ADDR(x) (x << 2) /* Hi6421 maximum register number */ #define HI6421_REG_MAX 0xFF /* Hi6421 OCP (over current protection) and DEB (debounce) control register */ #define HI6421_OCP_DEB_CTRL_REG HI6421_REG_TO_BUS_ADDR(0x51) #define HI6421_OCP_DEB_SEL_MASK 0x0C #define HI6421_OCP_DEB_SEL_8MS 0x00 #define HI6421_OCP_DEB_SEL_16MS 0x04 #define HI6421_OCP_DEB_SEL_32MS 0x08 #define HI6421_OCP_DEB_SEL_64MS 0x0C #define HI6421_OCP_EN_DEBOUNCE_MASK 0x02 #define HI6421_OCP_EN_DEBOUNCE_ENABLE 0x02 #define HI6421_OCP_AUTO_STOP_MASK 0x01 #define HI6421_OCP_AUTO_STOP_ENABLE 0x01 struct hi6421_pmic { struct regmap *regmap; }; enum hi6421_type { HI6421 = 0, HI6421_V530, }; #endif /* __HI6421_PMIC_H */ !ˆÀÉ ƒ|-=¿ÁÇ#¼!/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H #define _DT_BINDINGS_POWER_QCOM_RPMPD_H /* SA8775P Power Domain Indexes */ #define SA8775P_CX 0 #define SA8775P_CX_AO 1 #define SA8775P_DDR 2 #define SA8775P_EBI 3 #define SA8775P_GFX 4 #define SA8775P_LCX 5 #define SA8775P_LMX 6 #define SA8775P_MMCX 7 #define SA8775P_MMCX_AO 8 #define SA8775P_MSS 9 #define SA8775P_MX 10 #define SA8775P_MX_AO 11 #define SA8775P_MXC 12 #define SA8775P_MXC_AO 13 #define SA8775P_NSP0 14 #define SA8775P_NSP1 15 #define SA8775P_XO 16 /* SDM670 Power Domain Indexes */ #define SDM670_MX 0 #define SDM670_MX_AO 1 #define SDM670_CX 2 #define SDM670_CX_AO 3 #define SDM670_LMX 4 #define SDM670_LCX 5 #define SDM670_GFX 6 #define SDM670_MSS 7 /* SDM845 Power Domain Indexes */ #define SDM845_EBI 0 #define SDM845_MX 1 #define SDM845_MX_AO 2 #define SDM845_CX 3 #define SDM845_CX_AO 4 #define SDM845_LMX 5 #define SDM845_LCX 6 #define SDM845_GFX 7 #define SDM845_MSS 8 /* SDX55 Power Domain Indexes */ #define SDX55_MSS 0 #define SDX55_MX 1 #define SDX55_CX 2 /* SDX65 Power Domain Indexes */ #define SDX65_MSS 0 #define SDX65_MX 1 #define SDX65_MX_AO 2 #define SDX65_CX 3 #define SDX65_CX_AO 4 #define SDX65_MXC 5 /* SM6350 Power Domain Indexes */ #define SM6350_CX 0 #define SM6350_GFX 1 #define SM6350_LCX 2 #define SM6350_LMX 3 #define SM6350_MSS 4 #define SM6350_MX 5 /* SM6350 Power Domain Indexes */ #define SM6375_VDDCX 0 #define SM6375_VDDCX_AO 1 #define SM6375_VDDCX_VFL 2 #define SM6375_VDDMX 3 #define SM6375_VDDMX_AO 4 #define SM6375_VDDMX_VFL 5 #define SM6375_VDDGX 6 #define SM6375_VDDGX_AO 7 #define SM6375_VDD_LPI_CX 8 #define SM6375_VDD_LPI_MX 9 /* SM8150 Power Domain Indexes */ #define SM8150_MSS 0 #define SM8150_EBI 1 #define SM8150_LMX 2 #define SM8150_LCX 3 #define SM8150_GFX 4 #define SM8150_MX 5 #define SM8150_MX_AO 6 #define SM8150_CX 7 #define SM8150_CX_AO 8 #define SM8150_MMCX 9 #define SM8150_MMCX_AO 10 /* SM8250 Power Domain Indexes */ #define SM8250_CX 0 #define SM8250_CX_AO 1 #define SM8250_EBI 2 #define SM8250_GFX 3 #define SM8250_LCX 4 #define SM8250_LMX 5 #define SM8250_MMCX 6 #define SM8250_MMCX_AO 7 #define SM8250_MX 8 #define SM8250_MX_AO 9 /* SM8350 Power Domain Indexes */ #define SM8350_CX 0 #define SM8350_CX_AO 1 #define SM8350_EBI 2 #define SM8350_GFX 3 #define SM8350_LCX 4 #define SM8350_LMX 5 #define SM8350_MMCX 6 #define SM8350_MMCX_AO 7 #define SM8350_MX 8 #define SM8350_MX_AO 9 #define SM8350_MXC 10 #define SM8350_MXC_AO 11 #define SM8350_MSS 12 /* SM8450 Power Domain Indexes */ #define SM8450_CX 0 #define SM8450_CX_AO 1 #define SM8450_EBI 2 #define SM8450_GFX 3 #define SM8450_LCX 4 #define SM8450_LMX 5 #define SM8450_MMCX 6 #define SM8450_MMCX_AO 7 #define SM8450_MX 8 #define SM8450_