PNP0C0F
     %ˆÌË607Ê¿È _    %/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _LINUX_AHCI_REMAP_H
#define _LINUX_AHCI_REMAP_H

#include <linux/sizes.h>

#define AHCI_VSCAP		0xa4
#define AHCI_REMAP_CAP		0x800

/* device class code */
#define AHCI_REMAP_N_DCC	0x880

/* remap-device base relative to ahci-bar */
#define AHCI_REMAP_N_OFFSET	SZ_16K
#define AHCI_REMAP_N_SIZE	SZ_16K

#define AHCI_MAX_REMAP		3

static inline unsigned int ahci_remap_dcc(int i)
{
	return AHCI_REMAP_N_DCC + i * 0x80;
}

static inline unsigned int ahci_remap_base(int i)
{
	return AHCI_REMAP_N_OFFSET + i * AHCI_REMAP_N_SIZE;
}

#endif /* _LINUX_AHCI_REMAP_H */
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     )ˆÌË„Y|_Ê¿È ,€    )/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2003 Russell King, All Rights Reserved.
 *
 * This driver supports the following PXA CPU/SSP ports:-
 *
 *       PXA250     SSP
 *       PXA255     SSP, NSSP
 *       PXA26x     SSP, NSSP, ASSP
 *       PXA27x     SSP1, SSP2, SSP3
 *       PXA3xx     SSP1, SSP2, SSP3, SSP4
 */

#ifndef __LINUX_PXA2XX_SSP_H
#define __LINUX_PXA2XX_SSP_H

#include <linux/bits.h>
#include <linux/compiler_types.h>
#include <linux/io.h>
#include <linux/kconfig.h>
#include <linux/list.h>
#include <linux/types.h>

struct clk;
struct device;
struct device_node;

/*
 * SSP Serial Port Registers
 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
 */

#define SSCR0		(0x00)  /* SSP Control Register 0 */
#define SSCR1		(0x04)  /* SSP Control Register 1 */
#define SSSR		(0x08)  /* SSP Status Register */
#define SSITR		(0x0C)  /* SSP Interrupt Test Register */
#define SSDR		(0x10)  /* SSP Data Write/Data Read Register */

#define SSTO		(0x28)  /* SSP Time Out Register */
#define SSPSP		(0x2C)  /* SSP Programmable Serial Protocol */
#define SSTSA		(0x30)  /* SSP Tx Timeslot Active */
#define SSRSA		(0x34)  /* SSP Rx Timeslot Active */
#define SSTSS		(0x38)  /* SSP Timeslot Status */
#define SSACD		(0x3C)  /* SSP Audio Clock Divider */
#define SSACDD		(0x40)	/* SSP Audio Clock Dither Divider */

/* Common PXA2xx bits first */
#define SSCR0_DSS	GENMASK(3, 0)	/* Data Size Select (mask) */
#define SSCR0_DataSize(x)  ((x) - 1)	/* Data Size Select [4..16] */
#define SSCR0_FRF	GENMASK(5, 4)	/* FRame Format (mask) */
#define SSCR0_Motorola	(0x0 << 4)	/* Motorola's Serial Peripheral Interface (SPI) */
#define SSCR0_TI	(0x1 << 4)	/* Texas Instruments' Synchronous Serial Protocol (SSP) */
#define SSCR0_National	(0x2 << 4)	/* National Microwire */
#define SSCR0_ECS	BIT(6)		/* External clock select */
#define SSCR0_SSE	BIT(7)		/* Synchronous Serial Port Enable */
#define SSCR0_SCR(x)	((x) << 8)	/* Serial Clock Rate (mask) */

/* PXA27x, PXA3xx */
#define SSCR0_EDSS	BIT(20)		/* Extended data size select */
#define SSCR0_NCS	BIT(21)		/* Network clock select */
#define SSCR0_RIM	BIT(22)		/* Receive FIFO overrun interrupt mask */
#define SSCR0_TUM	BIT(23)		/* Transmit FIFO underrun interrupt mask */
#define SSCR0_FRDC	GENMASK(26, 24)	/* Frame rate divider control (mask) */
#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)	/* Time slots per frame [1..8] */
#define SSCR0_FPCKE	BIT(29)		/* FIFO packing enable */
#define SSCR0_ACS	BIT(30)		/* Audio clock select */
#define SSCR0_MOD	BIT(31)		/* Mode (normal or network) */

#define SSCR1_RIE	BIT(0)		/* Receive FIFO Interrupt Enable */
#define SSCR1_TIE	BIT(1)		/* Transmit FIFO Interrupt Enable */
#define SSCR1_LBM	BIT(2)		/* Loop-Back Mode */
#define SSCR1_SPO	BIT(3)		/* Motorola SPI SSPSCLK polarity setting */
#define SSCR1_SPH	BIT(4)		/* Motorola SPI SSPSCLK phase setting */
#define SSCR1_MWDS	BIT(5)		/* Microwire Transmit Data Size */

#define SSSR_ALT_FRM_MASK	GENMASK(1, 0)	/* Masks the SFRM signal number */
#define SSSR_TNF		BIT(2)		/* Transmit FIFO Not Full */
#define SSSR_RNE		BIT(3)		/* Receive FIFO Not Empty */
#define SSSR_BSY		BIT(4)		/* SSP Busy */
#define SSSR_TFS		BIT(5)		/* Transmit FIFO Service Request */
#define SSSR_RFS		BIT(6)		/* Receive FIFO Service Reques