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  +   €l–Ь4э( ©і( 	ЕЂfаB¦-яї„@л__†I|ҐЏ+ДГ ?ч     /* SPDX-License-Identifier: GPL-2.0 */
/*
 * Type definitions for the Microsoft hypervisor.
 */
#ifndef _HV_HVHDK_H
#define _HV_HVHDK_H

#include <linux/build_bug.h>

#include "hvhdk_mini.h"
#include "hvgdk.h"

/* Bits for dirty mask of hv_vp_register_page */
#define HV_X64_REGISTER_CLASS_GENERAL	0
#define HV_X64_REGISTER_CLASS_IP	1
#define HV_X64_REGISTER_CLASS_XMM	2
#define HV_X64_REGISTER_CLASS_SEGMENT	3
#define HV_X64_REGISTER_CLASS_FLAGS	4

#define HV_VP_REGISTER_PAGE_VERSION_1	1u

#define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT		7

union hv_vp_register_page_interrupt_vectors {
	u64 as_uint64;
	struct {
		u8 vector_count;
		u8 vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT];
	} __packed;
};

struct hv_vp_register_page {
	u16 version;
	u8 isvalid;
	u8 rsvdz;
	u32 dirty;

#if IS_ENABLED(CONFIG_X86)

	union {
		struct {
			/* General purpose registers
			 * (HV_X64_REGISTER_CLASS_GENERAL)
			 */
			union {
				struct {
					u64 rax;
					u64 rcx;
					u64 rdx;
					u64 rbx;
					u64 rsp;
					u64 rbp;
					u64 rsi;
					u64 rdi;
					u64 r8;
					u64 r9;
					u64 r10;
					u64 r11;
					u64 r12;
					u64 r13;
					u64 r14;
					u64 r15;
				} __packed;

				u64 gp_registers[16];
			};
			/* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */
			u64 rip;
			/* Flags (HV_X64_REGISTER_CLASS_FLAGS) */
			u64 rflags;
		} __packed;

		u64 registers[18];
	};
	/* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */
	union {
		struct {
			struct hv_u128 xmm0;
			struct hv_u128 xmm1;
			struct hv_u128 xmm2;
			struct hv_u128 xmm3;
			struct hv_u128 xmm4;
			struct hv_u128 xmm5;
		} __packed;

		struct hv_u128 xmm_registers[6];
	};
	/* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */
	union {
		struct {
			struct hv_x64_segment_register es;
			struct hv_x64_segment_register cs;
			struct hv_x64_segment_register ss;
			struct hv_x64_segment_register ds;
			struct hv_x64_segment_register fs;
			struct hv_x64_segment_register gs;
		} __packed;

		struct hv_x64_segment_register segment_registers[6];
	};
	/* Misc. control registers (cannot be set via this interface) */
	u64 cr0;
	u64 cr3;
	u64 cr4;
	u64 cr8;
	u64 efer;
	u64 dr7;
	union hv_x64_pending_interruption_register pending_interruption;
	union hv_x64_interrupt_state_register interrupt_state;
	u64 instruction_emulation_hints;
	u64 xfem;

	/*
	 * Fields from this point are not included in the register page save chunk.
	 * The reserved field is intended to maintain alignment for unsaved fields.
	 */
	u8 reserved1[0x100];

	/*
	 * Interrupts injected as part of HvCallDispatchVp.
	 */
	union hv_vp_register_page_interrupt_vectors interrupt_vectors;

#elif IS_ENABLED(CONFIG_ARM64)
	/* Not yet supported in ARM */
#endif
} __packed;

#define HV_PARTITION_PROCESSOR_FEATURES_BANKS 2

union hv_partition_processor_features {
	u64 as_uint64[HV_PARTITION_PROCESSOR_FEATURES_BANKS];
	struct {
		u64 sse3_support : 1;
		u64 lahf_sahf_support : 1;
		u64 ssse3_support : 1;
		u64 sse4_1_support : 1;
		u64 sse4_2_support : 1;
		u64 sse4a_support : 1;
		u64 xop_support : 1;
		u64 pop_cnt_support : 1;
		u64 cmpxchg16b_support : 1;
		u64 altmovcr8_support : 1;
		u64 lzcnt_support : 1;
		u64 mis_align_sse_support : 1;
		u64 mmx_ext_support : 1;
		u64 amd3dnow_support : 1;
		u64 extended_amd3dnow_support : 1;
		u64 page_1gb_support : 1;
		u64 aes_support : 1;
		u64 pclmulqdq_support : 1;
		u64 pcid_support : 1;
		u64 fma4_support : 1;
		u64 f16c_support : 1;
		u64 rd_rand_support : 1;
		u64 rd_wr_fs_gs_support : 1;
		u64 smep_support : 1;
		u64 enhanced_fast_string_support : 1;
		u64 bmi1_support : 1;
		u64 bmi2_support : 1;
		u64 hle_support_deprecated : 1;
		u64 rtm_support_deprecated : 1;
		u64 movbe_support : 1;
		u64 npiep1_support : 1;
		u64 dep_x87_fpu_save_support : 1;
		u64 rd_seed_support : 1;
		u64 adx_support : 1;
		u64 intel_prefetch_support : 1;
		u64 smap_support : 1;
		u64 hle_support : 1;
		u64 rtm_support : 1;
		u64 rdtscp_support : 1;
		u64 clflushopt_support : 1;
		u64 clwb_support : 1;
		u64 sha_support : 1;
		u64 x87_pointer