5 ߈ÐÕ 0¾Ò áˆÐÕ 0¾Ò ãˆÐÕ 0¾Ò åˆÐÕ 0¾Ò çˆÖÕ ƒqçCÔ¾Ò×ç/* SPDX-License-Identifier: GPL-2.0 */ /* * FPGA Framework * * Copyright (C) 2013-2016 Altera Corporation * Copyright (C) 2017 Intel Corporation */ #ifndef _LINUX_FPGA_MGR_H #define _LINUX_FPGA_MGR_H #include #include struct fpga_manager; struct sg_table; /** * enum fpga_mgr_states - fpga framework states * @FPGA_MGR_STATE_UNKNOWN: can't determine state * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up * @FPGA_MGR_STATE_RESET: FPGA in reset state * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage * @FPGA_MGR_STATE_WRITE: writing image to FPGA * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating */ enum fpga_mgr_states { /* default FPGA states */ FPGA_MGR_STATE_UNKNOWN, FPGA_MGR_STATE_POWER_OFF, FPGA_MGR_STATE_POWER_UP, FPGA_MGR_STATE_RESET, /* getting an image for loading */ FPGA_MGR_STATE_FIRMWARE_REQ, FPGA_MGR_STATE_FIRMWARE_REQ_ERR, /* write sequence: init, write, complete */ FPGA_MGR_STATE_WRITE_INIT, FPGA_MGR_STATE_WRITE_INIT_ERR, FPGA_MGR_STATE_WRITE, FPGA_MGR_STATE_WRITE_ERR, FPGA_MGR_STATE_WRITE_COMPLETE, FPGA_MGR_STATE_WRITE_COMPLETE_ERR, /* fpga is programmed and operating */ FPGA_MGR_STATE_OPERATING, }; /** * DOC: FPGA Manager flags * * Flags used in the &fpga_image_info->flags field * * %FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported * * %FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting * * %FPGA_MGR_ENCRYPTED_BITSTREAM: indicates bitstream is encrypted * * %FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first * * %FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed */ #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) /** * struct fpga_image_info - information specific to an FPGA image * @flags: boolean flags as defined above * @enable_timeout_us: maximum time to enable traffic through bridge (uSec) * @disable_timeout_us: maximum time to disable traffic through bridge (uSec) * @config_complete_timeout_us: maximum time for FPGA to switch to operating * status in the write_complete op. * @firmware_name: name of FPGA image firmware file * @sgt: scatter/gather table containing FPGA image * @buf: contiguous buffer containing FPGA image * @count: size of buf * @region_id: id of target region * @dev: device that owns this * @overlay: Device Tree overlay */ struct fpga_image_info { u32 flags; u32 enable_timeout_us; u32 disable_timeout_us; u32 config_complete_timeout_us; char *firmware_name; struct sg_table *sgt; const char *buf; size_t count; int region_id; struct device *dev; #ifdef CONFIG_OF struct device_node *overlay; #endif }; /** * struct fpga_manager_ops - ops for low level fpga manager drivers * @initial_header_size: Maximum number of bytes that should be passed into write_init * @state: returns an enum value of the FPGA's state * @status: returns status of the FPGA, including reconfiguration error code * @write_init: prepare the FPGA to receive confuration data * @write: write count bytes of configuration data to the FPGA * @write_sg: write the scatter list of configuration data to the FPGA * @write_complete: set FPGA to operating state after writing is done * @fpga_remove: optional: Set FPGA into a specific state during driver remove * @groups: optional attribute groups. * * fpga_manager_ops are the low level