auto =ˆÄÇ ƒtAwÃÀÅ1=/* SPDX-License-Identifier: GPL-2.0-only */ /* * linux/include/linux/mtd/onenand_regs.h * * OneNAND Register header file * * Copyright (C) 2005-2007 Samsung Electronics * Kyungmin Park */ #ifndef __ONENAND_REG_H #define __ONENAND_REG_H /* Memory Address Map Translation (Word order) */ #define ONENAND_MEMORY_MAP(x) ((x) << 1) /* * External BufferRAM area */ #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000) #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200) #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010) /* * OneNAND Registers */ #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000) #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001) #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002) #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003) #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004) #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005) #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006) #define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100) #define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101) #define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102) #define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103) #define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104) #define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105) #define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106) #define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107) #define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200) #define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220) #define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221) #define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222) #define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240) #define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241) #define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C) #define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D) #define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E) #define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00) #define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01) #define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02) #define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03) #define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04) #define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05) #define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06) #define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07) #define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08) /* * Device ID Register F001h (R) */ #define DEVICE_IS_FLEXONENAND (1 << 9) #define FLEXONENAND_PI_MASK (0x3ff) #define FLEXONENAND_PI_UNLOCK_SHIFT (14) #define ONENAND_DEVICE_DENSITY_MASK (0xf) #define ONENAND_DEVICE_DENSITY_SHIFT (4) #define ONENAND_DEVICE_IS_DDP (1 << 3) #define ONENAND_DEVICE_IS_DEMUX (1 << 2) #define ONENAND_DEVICE_VCC_MASK (0x3) #define ONENAND_DEVICE_DENSITY_512Mb (0x002) #define ONENAND_DEVICE_DENSITY_1Gb (0x003) #define ONENAND_DEVICE_DENSITY_2Gb (0x004) #define ONENAND_DEVICE_DENSITY_4Gb (0x005) #define ONENAND_DEVICE_DENSITY_8Gb (0x006) /* * Version ID Register F002h (R) */ #define ONENAND_VERSION_PROCESS_SHIFT (8) /* * Technology Register F006h (R) */ #define ONENAND_TECHNOLOGY_IS_MLC (1 << 0) /* * Start Address 1 F100h (R/W) & Start Address 2 F101h (R/W) */ #define ONENAND_DDP_SHIFT (15) #define ONENAND_DDP_CHIP0 (0) #define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT) /* * Start Address 8 F107h (R/W) */ /* Note: It's actually 0x3f in case of SLC */ #define ONENAND_FPA_MASK (0x7f) #define ONENAND_FPA_SHIFT (2) #define ONENAND_FSA_MASK (0x03) /* * Start Buffer Register F200h (R/W) */ #define ONENAND_BSA_MASK (0x03) #define ONENAND_BSA_SHIFT (8) #define ONENAND_BSA_BOOTRAM (0 << 2) #define ONENAND_BSA_DATARAM0 (2 << 2) #define ONENAND_BSA_DATARAM1 (3 << 2) /* Note: It's actually 0x03 in case of SLC */ #define ONENAND_BSC_MASK (0x07) /* * Command Register F220h (R/W) */ #define ONENAND_CMD_READ (0x00) #define ONENAND_