0000:00:0f )ˆÏÎ ƒ}—šÍ¿Ë$¨)/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2019 Rockchip Electronics Co. Ltd. * Author: Finley Xiao */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H /* core clocks */ #define PLL_APLL 1 #define PLL_DPLL 2 #define PLL_VPLL0 3 #define PLL_VPLL1 4 #define ARMCLK 5 /* sclk (special clocks) */ #define USB480M 14 #define SCLK_RTC32K 15 #define SCLK_PVTM_CORE 16 #define SCLK_UART0 17 #define SCLK_UART1 18 #define SCLK_UART2 19 #define SCLK_UART3 20 #define SCLK_UART4 21 #define SCLK_I2C0 22 #define SCLK_I2C1 23 #define SCLK_I2C2 24 #define SCLK_I2C3 25 #define SCLK_PWM0 26 #define SCLK_SPI0 27 #define SCLK_SPI1 28 #define SCLK_SPI2 29 #define SCLK_TIMER0 30 #define SCLK_TIMER1 31 #define SCLK_TIMER2 32 #define SCLK_TIMER3 33 #define SCLK_TIMER4 34 #define SCLK_TIMER5 35 #define SCLK_TSADC 36 #define SCLK_SARADC 37 #define SCLK_OTP 38 #define SCLK_OTP_USR 39 #define SCLK_CPU_BOOST 40 #define SCLK_CRYPTO 41 #define SCLK_CRYPTO_APK 42 #define SCLK_NANDC_DIV 43 #define SCLK_NANDC_DIV50 44 #define SCLK_NANDC 45 #define SCLK_SDMMC_DIV 46 #define SCLK_SDMMC_DIV50 47 #define SCLK_SDMMC 48 #define SCLK_SDMMC_DRV 49 #define SCLK_SDMMC_SAMPLE 50 #define SCLK_SDIO_DIV 51 #define SCLK_SDIO_DIV50 52 #define SCLK_SDIO 53 #define SCLK_SDIO_DRV 54 #define SCLK_SDIO_SAMPLE 55 #define SCLK_EMMC_DIV 56 #define SCLK_EMMC_DIV50 57 #define SCLK_EMMC 58 #define SCLK_EMMC_DRV 59 #define SCLK_EMMC_SAMPLE 60 #define SCLK_SFC 61 #define SCLK_OTG_ADP 62 #define SCLK_MAC_SRC 63 #define SCLK_MAC 64 #define SCLK_MAC_REF 65 #define SCLK_MAC_RX_TX 66 #define SCLK_MAC_RMII 67 #define SCLK_DDR_MON_TIMER 68 #define SCLK_DDR_MON 69 #define SCLK_DDRCLK 70 #define SCLK_PMU 71 #define SCLK_USBPHY_REF 72 #define SCLK_WIFI 73 #define SCLK_PVTM_PMU 74 #define SCLK_PDM 75 #define SCLK_I2S0_8CH_TX 76 #define SCLK_I2S0_8CH_TX_OUT 77 #define SCLK_I2S0_8CH_RX 78 #define SCLK_I2S0_8CH_RX_OUT 79 #define SCLK_I2S1_8CH_TX 80 #define SCLK_I2S1_8CH_TX_OUT 81 #define SCLK_I2S1_8CH_RX 82 #define SCLK_I2S1_8CH_RX_OUT 83 #define SCLK_I2S2_8CH_TX 84 #define SCLK_I2S2_8CH_TX_OUT 85 #define SCLK_I2S2_8CH_RX 86 #define SCLK_I2S2_8CH_RX_OUT 87 #define SCLK_I2S3_8CH_TX 88 #define SCLK_I2S3_8CH_TX_OUT 89 #define SCLK_I2S3_8CH_RX 90 #define SCLK_I2S3_8CH_RX_OUT 91 #define SCLK_I2S0_2CH 92 #define SCLK_I2S0_2CH_OUT 93 #define SCLK_I2S1_2CH 94 #define SCLK_I2S1_2CH_OUT 95 #define SCLK_SPDIF_TX_DIV 96 #define SCLK_SPDIF_TX_DIV50 97 #define SCLK_SPDIF_TX 98 #define SCLK_SPDIF_RX_DIV 99 #define SCLK_SPDIF_RX_DIV50 100 #define SCLK_SPDIF_RX 101 #define SCLK_I2S0_8CH_TX_MUX 102 #define SCLK_I2S0_8CH_RX_MUX 103 #define SCLK_I2S1_8CH_TX_MUX 104 #define SCLK_I2S1_8CH_RX_MUX 105 #define SCLK_I2S2_8CH_TX_MUX 106 #define SCLK_I2S2_8CH_RX_MUX 107 #define SCLK_I2S3_8CH_TX_MUX 108 #define SCLK_I2S3_8CH_RX_MUX 109 #define SCLK_I2S0_8CH_TX_SRC 110 #define SCLK_I2S0_8CH_RX_SRC 111 #define SCLK_I2S1_8CH_TX_SRC 112 #define SCLK_I2S1_8CH_RX_SRC 113 #define SCLK_I2S2_8CH_TX_SRC 114 #define SCLK_I2S2_8CH_RX_SRC 115 #define SCLK_I2S3_8CH_TX_SRC 116 #define SCLK_I2S3_8CH_RX_SRC 117 #define SCLK_I2S0_2CH_SRC 118 #define SCLK_I2S1_2CH_SRC 119 #define SCLK_PWM1 120 #define SCLK_PWM2 121 #define SCLK_OWIRE 122 /* dclk */ #define DCLK_VOP 125 /* aclk */ #define ACLK_BUS_SRC 130 #define ACLK_BUS 131 #define ACLK_PERI_SRC 132 #define ACLK_PERI 133 #define ACLK_MAC 134 #define ACLK_CRYPTO 135 #define ACLK_VOP 136 #define ACLK_GIC 137 #define ACLK_DMAC0 138 #define ACLK_DMAC1 139 /* hclk */ #define HCLK_BUS 150 #define HCLK_PERI 151 #define HCLK_AUDIO 152 #define HCLK_NANDC 153 #define HCLK_SDMMC 154 #define HCLK_SDIO 155 #define HCLK_EMMC 156 #define HCLK_SFC 157 #define HCLK_OTG 158 #define HCLK_HOST 159 #define HCLK_HOST_ARB 160 #define HCLK_PDM 161 #define HCLK_SPDIFTX 162 #define HCLK_SPDIFRX 163 #define HCLK_I2S0_8CH 164 #define HCLK_I2S1_8CH 165 #define HCLK_I2S2_8CH 166 #define HCLK_I2S3_8CH