3000 *l4( (  fB- w_I|+I/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2022 HiSilicon Limited. */ #ifndef _KERNEL_DMA_BENCHMARK_H #define _KERNEL_DMA_BENCHMARK_H #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 #define DMA_MAP_MAX_TRANS_DELAY (10 * NSEC_PER_MSEC) #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 #define DMA_MAP_FROM_DEVICE 2 struct map_benchmark { __u64 avg_map_100ns; /* average map latency in 100ns */ __u64 map_stddev; /* standard deviation of map latency */ __u64 avg_unmap_100ns; /* as above */ __u64 unmap_stddev; __u32 threads; /* how many threads will do map/unmap in parallel */ __u32 seconds; /* how long the test will last */ __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ __u32 dma_trans_ns; /* time for DMA transmission in ns */ __u32 granule; /* how many PAGE_SIZE will do map/unmap once a time */ }; #endif /* _KERNEL_DMA_BENCHMARK_H */ 0li~ h8Eq41h q_ub &=Ly[Ͽ7zXZi"6!t/'](R 6#[=ƹVtQ-}a":L{u$ǛbЮr}0,kjW]kKtM? O/%5À>}Z櫚vsk (\pJCGxf['@`!F*8vX&T6 [e]Na s ~>@Ch%cxEOCb}5`rD&)/`1=?3mhF"w(Ғ;aR @">9bR)cH^tpzȽ_E^2!մm!=5а;%&uځҁ 5\jd7;v=&7El7|FXV?܁dCw2Lula4S@Ehx0 Z*C_q#hW]}Pׁ0 "UmgIjgS3!IWf:Voa xHf2Cռw}v~ 3~$Tת W*GJ*hJAءzm3$fi2cJ50Ո딑Bz~Eot]I=5LG HΙXcB;7dK.wcV洇i.q) qD4FM]bei6-BB^?PNb?%~dW>E!-h[ qLЄh-)|"s%މ\0Z;#l!K]3U\cF@$%OaiքE̲3T'& hP BEG 6sO.Zs~K6ej $R-))YQSG}q2cE!i%K~W%Pg+AQE3# 6JrZm!5mrn$ GV^x@8vctU6яз'Pw*ߚ".=k %yh*"W MkȶwTq?#X+p-y 3r<`j}򪀴4tbLaq7g1qQ(}4A"쇓My~`g;>$$[4nR8q8&)56r&$] Qc# I,SDR\p*V?`LO6P_)~q}k= [g0&+ԡ)U6*m7CuA ϋÇ@/