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<h1>Index of /anon_sym/anon/sys/class/input/event2/subsystem/input5/event4</h1>
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<tr><td valign="top">&nbsp;</td><td><a href="dev">dev</a>                    </td><td align="right">2026-10-11 20:45  </td><td align="right">4.0K</td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="device/">device/</a>                </td><td align="right">2026-10-10 19:05  </td><td align="right">  - </td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="power/">power/</a>                 </td><td align="right">2026-10-11 20:42  </td><td align="right">  - </td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="subsystem/">subsystem/</a>             </td><td align="right">2026-10-11 12:29  </td><td align="right">  - </td><td>&nbsp;</td></tr>
<tr><td valign="top">&nbsp;</td><td><a href="uevent">uevent</a>                 </td><td align="right">2026-10-11 20:45  </td><td align="right">4.0K</td><td>&nbsp;</td></tr>
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  A   ˆl–Ü4ý( ©³( 	Å€fàB¦-ÿ¿ƒ�·_†I|¥�+a–Ðz¾””ÔD¨ 	Å �9p S�ÿÃ Ÿ    /* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright 2020 NXP
 */

#ifndef DT_BINDING_RESET_IMX8MP_H
#define DT_BINDING_RESET_IMX8MP_H

#define IMX8MP_RESET_A53_CORE_POR_RESET0	0
#define IMX8MP_RESET_A53_CORE_POR_RESET1	1
#define IMX8MP_RESET_A53_CORE_POR_RESET2	2
#define IMX8MP_RESET_A53_CORE_POR_RESET3	3
#define IMX8MP_RESET_A53_CORE_RESET0		4
#define IMX8MP_RESET_A53_CORE_RESET1		5
#define IMX8MP_RESET_A53_CORE_RESET2		6
#define IMX8MP_RESET_A53_CORE_RESET3		7
#define IMX8MP_RESET_A53_DBG_RESET0		8
#define IMX8MP_RESET_A53_DBG_RESET1		9
#define IMX8MP_RESET_A53_DBG_RESET2		10
#define IMX8MP_RESET_A53_DBG_RESET3		11
#define IMX8MP_RESET_A53_ETM_RESET0		12
#define IMX8MP_RESET_A53_ETM_RESET1		13
#define IMX8MP_RESET_A53_ETM_RESET2		14
#define IMX8MP_RESET_A53_ETM_RESET3		15
#define IMX8MP_RESET_A53_SOC_DBG_RESET		16
#define IMX8MP_RESET_A53_L2RESET		17
#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST	18
#define IMX8MP_RESET_OTG1_PHY_RESET		19
#define IMX8MP_RESET_OTG2_PHY_RESET		20
#define IMX8MP_RESET_SUPERMIX_RESET		21
#define IMX8MP_RESET_AUDIOMIX_RESET		22
#define IMX8MP_RESET_MLMIX_RESET		23
#define IMX8MP_RESET_PCIEPHY			24
#define IMX8MP_RESET_PCIEPHY_PERST		25
#define IMX8MP_RESET_PCIE_CTRL_APPS_EN		26
#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF	27
#define IMX8MP_RESET_HDMI_PHY_APB_RESET		28
#define IMX8MP_RESET_MEDIA_RESET		29
#define IMX8MP_RESET_GPU2D_RESET		30
#define IMX8MP_RESET_GPU3D_RESET		31
#define IMX8MP_RESET_GPU_RESET			32
#define IMX8MP_RESET_VPU_RESET			33
#define IMX8MP_RESET_VPU_G1_RESET		34
#define IMX8MP_RESET_VPU_G2_RESET		35
#define IMX8MP_RESET_VPUVC8KE_RESET		36
#define IMX8MP_RESET_NOC_RESET			37

#define IMX8MP_RESET_NUM			38

#endif
     	ˆÀÁ„Íï¿¾Ã ?÷     	/* SPDX-License-Identifier: GPL-2.0
 *
 * soc-component.h
 *
 * Copyright (C) 2019 Renesas Electronics Corp.
 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 */
#ifndef __SOC_COMPONENT_H
#define __SOC_COMPONENT_H

#include <sound/soc.h>

/*
 * Component probe and remove ordering levels for components with runtime
 * dependencies.
 */
#define SND_SOC_COMP_ORDER_FIRST	-2
#define SND_SOC_COMP_ORDER_EARLY	-1
#define SND_SOC_COMP_ORDER_NORMAL	 0
#define SND_SOC_COMP_ORDER_LATE		 1
#define SND_SOC_COMP_ORDER_LAST		 2

#define for_each_comp_order(order)		\
	for (