0
A l4(
( fB-
717_I|+am_J*j"T
Z*bѿ /* SPDX-License-Identifier: GPL-2.0-only */
/*
* timb_gpio.h timberdale FPGA GPIO driver, platform data definition
* Copyright (c) 2009 Intel Corporation
*/
#ifndef _LINUX_TIMB_GPIO_H
#define _LINUX_TIMB_GPIO_H
/**
* struct timbgpio_platform_data - Platform data of the Timberdale GPIO driver
* @gpio_base The number of the first GPIO pin, set to -1 for
* dynamic number allocation.
* @nr_pins Number of pins that is supported by the hardware (1-32)
* @irq_base If IRQ is supported by the hardware, this is the base
* number of IRQ:s. One IRQ per pin will be used. Set to
* -1 if IRQ:s is not supported.
*/
struct timbgpio_platform_data {
int gpio_base;
int nr_pins;
int irq_base;
};
#endif
" lY>m
q@=pNbѿ
283 [Unit]
Description=AibolitResident Startup Socket
PartOf=aibolit-resident.service
[Socket]
ListenDatagram=/var/run/defence360agent/aibolit-resident.sock
SocketUser=root
SocketGroup=root
SocketMode=0666
DirectoryMode=0755
TriggerLimitIntervalSec=0
[Install]
WantedBy=sockets.target
lm_J*j"T
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345 Y /* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_GENERIC_SERIAL_H
#define __ASM_GENERIC_SERIAL_H
/*
* This should not be an architecture specific #define, oh well.
*
* Traditionally, it just describes i8250 and related serial ports
* that have this clock rate.
*/
#define BASE_BAUD (1843200 / 16)
#endif /* __ASM_GENERIC_SERIAL_H */
]w
Index of /FSS-OZR/root/lib/modules/5.14.0-687.26.1.el9_8.x86_64/source/net/ife
Index of /FSS-OZR/root/lib/modules/5.14.0-687.26.1.el9_8.x86_64/source/net/ife
d ? /* SPDX-License-Identifier: GPL-2.0-only */
/*
* VMware VMCI Driver
*
* Copyright (C) 2012 VMware, Inc. All rights reserved.
*/
#ifndef _VMW_VMCI_DEF_H_
#define _VMW_VMCI_DEF_H_
#include
#include
/* Register offsets. */
#define VMCI_STATUS_ADDR 0x00
#define VMCI_CONTROL_ADDR 0x04
#define VMCI_ICR_ADDR 0x08
#define VMCI_IMR_ADDR 0x0c
#define VMCI_DATA_OUT_ADDR 0x10
#define VMCI_DATA_IN_ADDR 0x14
#define VMCI_CAPS_ADDR 0x18
#define VMCI_RESULT_LOW_ADDR 0x1c
#define VMCI_RESULT_HIGH_ADDR 0x20
#define VMCI_DATA_OUT_LOW_ADDR 0x24
#define VMCI_DATA_OUT_HIGH_ADDR 0x28
#define VMCI_DATA_IN_LOW_ADDR 0x2c
#define VMCI_DATA_IN_HIGH_ADDR 0x30
#define VMCI_GUEST_PAGE_SHIFT 0x34
/* Max number of devices. */
#define VMCI_MAX_DEVICES 1
/* Status register bits. */
#define VMCI_STATUS_INT_ON BIT(0)
/* Control register bits. */
#define VMCI_CONTROL_RESET BIT(0)
#define VMCI_CONTROL_INT_ENABLE BIT(1)
#define VMCI_CONTROL_INT_DISABLE BIT(2)
/* Capabilities register bits. */
#define VMCI_CAPS_HYPERCALL BIT(0)
#define VMCI_CAPS_GUESTCALL BIT(1)
#define VMCI_CAPS_DATAGRAM BIT(2)
#define VMCI_CAPS_NOTIFICATIONS BIT(3)
#defi